occheung
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

sayma_rtm: connect attenuator shift registers in series

This commit is contained in:
Sebastien Bourdeauducq 2019-12-20 18:58:31 +08:00
parent c5137eeb62
commit b7f1623197
1 changed files with 8 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
artiq/gateware/targets/sayma_rtm.py
View File

@ -203,16 +203,22 @@ class Satellite(_SatelliteBase):
phy = ttl_serdes_7series.Output_8X(platform.request("basemod{}_rfsw".format(bm), i)) phy = ttl_serdes_7series.Output_8X(platform.request("basemod{}_rfsw".format(bm), i))
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
print("BaseMod{} attenuator starting at RTIO channel 0x{:06x}" print("BaseMod{} attenuator starting at RTIO channel 0x{:06x}"
.format(bm, len(rtio_channels))) .format(bm, len(rtio_channels)))
basemod_att = platform.request("basemod{}_att".format(bm)) basemod_att = platform.request("basemod{}_att".format(bm))
for name in "rst_n clk mosi le".split(): for name in "rst_n clk le".split():
signal = getattr(basemod_att, name) signal = getattr(basemod_att, name)
for i in range(len(signal)): for i in range(len(signal)):
phy = ttl_simple.Output(signal[i]) phy = ttl_simple.Output(signal[i])
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
phy = ttl_simple.InOut(basemod_att.miso) phy = ttl_simple.Output(basemod_att.mosi[0])
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
for i in range(3):
self.comb += basemod_att.mosi[i+1].eq(basemod_att.miso[i])
phy = ttl_simple.InOut(basemod_att.miso[3])
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))