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test_i2c: port to NAC3

This commit is contained in:
Sebastien Bourdeauducq 2022-06-06 22:55:34 +08:00
parent cb68ed9f1d
commit b77f6886be
1 changed files with 14 additions and 1 deletions
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15
artiq/test/coredevice/test_i2c.py
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@ -3,14 +3,23 @@ import os, unittest
from artiq.experiment import * from artiq.experiment import *
from artiq.test.hardware_testbench import ExperimentCase from artiq.test.hardware_testbench import ExperimentCase
from artiq.coredevice.exceptions import I2CError from artiq.coredevice.exceptions import I2CError
from artiq.coredevice.core import Core
from artiq.coredevice.i2c import I2CSwitch, i2c_read_byte from artiq.coredevice.i2c import I2CSwitch, i2c_read_byte
@nac3
class I2CSwitchTest(EnvExperiment): class I2CSwitchTest(EnvExperiment):
core: KernelInvariant[Core]
i2c_switch: KernelInvariant[I2CSwitch]
def build(self): def build(self):
self.setattr_device("core") self.setattr_device("core")
self.setattr_device("i2c_switch") self.setattr_device("i2c_switch")
@rpc
def set_passed(self, passed: bool):
self.set_dataset("passed", passed)
@kernel @kernel
def run(self): def run(self):
passed = True passed = True
@ -20,10 +29,14 @@ class I2CSwitchTest(EnvExperiment):
# otherwise we cannot guarantee exact readback values # otherwise we cannot guarantee exact readback values
if i2c_read_byte(self.i2c_switch.busno, self.i2c_switch.address) != 1 << i: if i2c_read_byte(self.i2c_switch.busno, self.i2c_switch.address) != 1 << i:
passed = False passed = False
self.set_dataset("passed", passed) self.set_passed(passed)
@nac3
class NonexistentI2CBus(EnvExperiment): class NonexistentI2CBus(EnvExperiment):
core: KernelInvariant[Core]
broken_switch: KernelInvariant[I2CSwitch]
def build(self): def build(self):
self.setattr_device("core") self.setattr_device("core")
self.setattr_device("i2c_switch") # HACK: only run this test on boards with I2C self.setattr_device("i2c_switch") # HACK: only run this test on boards with I2C