forked from M-Labs/artiq
rename to coeff base and shorter write16
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@ -45,7 +45,7 @@ PHASER_ADDR_SERVO_CFG0 = 0x30
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PHASER_ADDR_SERVO_CFG1 = 0x31
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# 0x32 - 0x61 ab regs
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PHASER_ADDR_SERVO_AB_BASE = 0x32
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PHASER_ADDR_SERVO_COEFFICIENTS_BASE = 0x32
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# 0x62 - 0x71 offset regs
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PHASER_ADDR_SERVO_OFFSET_BASE = 0x62
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@ -418,10 +418,8 @@ class Phaser:
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@kernel
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def write16(self, addr, data: TInt32):
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"""Write 16 bit to a sequence of FPGA registers."""
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byte = data >> 8
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self.write8(addr, byte)
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byte = data & 0xFF
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self.write8(addr + 1, byte)
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self.write8(addr, data >> 8)
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self.write8(addr + 1, data)
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@kernel
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def write32(self, addr, data: TInt32):
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