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analyzer: drive wishbone cyc signal

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Sebastien Bourdeauducq 2016-03-15 19:46:12 +08:00
parent a142d403ea
commit b5ec979db3
1 changed files with 1 additions and 0 deletions
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artiq/gateware/rtio/analyzer.py
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@ -175,6 +175,7 @@ class DMAWriter(Module, AutoCSR):
# # #
self.comb += [
membus.cyc.eq(self.sink.stb),
membus.stb.eq(self.sink.stb),
self.sink.ack.eq(membus.ack),
membus.we.eq(1),