analyzer: drive wishbone cyc signal

2016-03-15 19:46:12 +08:00 · 2016-03-15 19:46:12 +08:00 · b5ec979db3
commit b5ec979db3
parent a142d403ea
1 changed files with 1 additions and 0 deletions
--- a/artiq/gateware/rtio/analyzer.py
+++ b/artiq/gateware/rtio/analyzer.py
@ -175,6 +175,7 @@ class DMAWriter(Module, AutoCSR):
        # # #

        self.comb += [
+            membus.cyc.eq(self.sink.stb),
            membus.stb.eq(self.sink.stb),
            self.sink.ack.eq(membus.ack),
            membus.we.eq(1),