forked from M-Labs/artiq
sayma: add sysref sampler to DRTIO master
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07bcdfd91e
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b28ff587c5
@ -309,6 +309,12 @@ class Master(MiniSoC, AMPSoC, RTMCommon):
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.submodules.ad9154_crg = jesd204_tools.UltrascaleCRG(platform)
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self.csr_devices.append("ad9154_crg")
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.ad9154_crg.cd_jesd.clk)
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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@ -325,6 +331,10 @@ class Master(MiniSoC, AMPSoC, RTMCommon):
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[self.rtio_core.cri] + drtio_cri)
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self.register_kernel_cpu_csrdevice("cri_con")
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self.submodules.sysref_sampler = jesd204_tools.SysrefSampler(
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self.rtio_core.coarse_ts, self.ad9154_crg.jref)
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self.csr_devices.append("sysref_sampler")
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class Satellite(BaseSoC, RTMCommon):
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mem_map = {
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