forked from M-Labs/artiq
kasli: add SYSU variant and device_db
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1c57d27ae2
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@ -0,0 +1,125 @@
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core_addr = "kasli-1.lab.m-labs.hk"
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device_db = {
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"core": {
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"type": "local",
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"module": "artiq.coredevice.core",
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"class": "Core",
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"arguments": {"host": core_addr, "ref_period": 1e-9}
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},
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"core_log": {
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"type": "controller",
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"host": "::1",
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"port": 1068,
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"command": "aqctl_corelog -p {port} --bind {bind} " + core_addr
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},
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"core_cache": {
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"type": "local",
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"module": "artiq.coredevice.cache",
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"class": "CoreCache"
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},
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"core_dma": {
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"type": "local",
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"module": "artiq.coredevice.dma",
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"class": "CoreDMA"
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},
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"i2c_switch0": {
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"type": "local",
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"module": "artiq.coredevice.i2c",
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"class": "PCA9548",
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"arguments": {"address": 0xe0}
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},
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"i2c_switch1": {
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"type": "local",
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"module": "artiq.coredevice.i2c",
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"class": "PCA9548",
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"arguments": {"address": 0xe2}
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},
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}
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for i in range(40):
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device_db["ttl" + str(i)] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLInOut",
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"arguments": {"channel": i},
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}
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device_db.update(
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spi_urukul0={
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"type": "local",
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"module": "artiq.coredevice.spi2",
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"class": "SPIMaster",
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"arguments": {"channel": 40}
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},
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ttl_urukul0_io_update={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 41}
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},
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ttl_urukul0_sw0={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 42}
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},
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ttl_urukul0_sw1={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 43}
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},
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ttl_urukul0_sw2={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 44}
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},
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ttl_urukul0_sw3={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 45}
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},
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urukul0_cpld={
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"type": "local",
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"module": "artiq.coredevice.urukul",
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"class": "CPLD",
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"arguments": {
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"spi_device": "spi_urukul0",
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"io_update_device": "ttl_urukul0_io_update",
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"refclk": 125e6,
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"clk_sel": 0
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}
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}
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)
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for i in range(4):
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device_db["urukul0_ch" + str(i)] = {
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"type": "local",
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"module": "artiq.coredevice.ad9910",
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"class": "AD9910",
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"arguments": {
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"pll_n": 32,
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"chip_select": 4 + i,
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"cpld_device": "urukul0_cpld",
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"sw_device": "ttl_urukul0_sw" + str(i)
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}
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}
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device_db.update(
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led0={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 46}
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},
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led1={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 47}
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}
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)
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@ -0,0 +1,21 @@
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from artiq.experiment import *
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class IdleKernel(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.setattr_device("led0")
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@kernel
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def run(self):
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start_time = now_mu() + self.core.seconds_to_mu(500*ms)
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while self.core.get_rtio_counter_mu() < start_time:
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pass
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self.core.reset()
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while True:
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self.led0.pulse(250*ms)
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delay(125*ms)
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self.led0.pulse(125*ms)
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delay(125*ms)
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self.led0.pulse(125*ms)
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delay(250*ms)
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@ -0,0 +1,49 @@
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from artiq.experiment import *
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class UrukulTest(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.setattr_device("urukul0_cpld")
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self.setattr_device("urukul0_ch0")
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self.setattr_device("urukul0_ch1")
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self.setattr_device("urukul0_ch2")
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self.setattr_device("urukul0_ch3")
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self.setattr_device("led0")
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@kernel
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def run(self):
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self.core.reset()
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self.led0.on()
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delay(5*ms)
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self.led0.off()
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self.urukul0_cpld.init()
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self.urukul0_ch0.init()
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self.urukul0_ch1.init()
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self.urukul0_ch2.init()
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self.urukul0_ch3.init()
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delay(1000*us)
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self.urukul0_ch0.set(100*MHz)
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self.urukul0_ch0.sw.on()
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self.urukul0_ch0.set_att(10.)
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delay(1000*us)
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self.urukul0_ch1.set(10*MHz, 0.5)
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self.urukul0_ch1.sw.on()
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self.urukul0_ch1.set_att(0.)
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delay(1000*us)
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self.urukul0_ch2.set(400*MHz)
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self.urukul0_ch2.sw.on()
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self.urukul0_ch2.set_att(0.)
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delay(1000*us)
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self.urukul0_ch3.set(1*MHz)
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self.urukul0_ch3.sw.on()
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self.urukul0_ch3.set_att(20.)
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while True:
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self.urukul0_ch0.sw.pulse(5*ms)
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delay(5*ms)
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@ -304,6 +304,59 @@ class Opticlock(_StandaloneBase):
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self.add_rtio(rtio_channels)
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class SYSU(_StandaloneBase):
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def __init__(self, **kwargs):
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_StandaloneBase.__init__(self, **kwargs)
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self.config["SI5324_AS_SYNTHESIZER"] = None
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self.config["RTIO_FREQUENCY"] = "125.0"
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platform = self.platform
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platform.add_extension(_urukul("eem1", "eem0"))
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platform.add_extension(_dio("eem2"))
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platform.add_extension(_dio("eem3"))
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platform.add_extension(_dio("eem4"))
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platform.add_extension(_dio("eem5"))
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platform.add_extension(_dio("eem6"))
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# EEM clock fan-out from Si5324, not MMCX
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self.comb += platform.request("clk_sel").eq(1)
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rtio_channels = []
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for i in range(40):
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eem_offset, port = divmod(i, 8)
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pads = platform.request("eem{}".format(2 + eem_offset), port)
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phy = ttl_serdes_7series.InOut_8X(pads.p, pads.n)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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phy = spi2.SPIMaster(self.platform.request("eem1_spi_p"),
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self.platform.request("eem1_spi_n"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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pads = platform.request("eem1_dds_reset")
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self.specials += DifferentialOutput(0, pads.p, pads.n)
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for signal in "io_update sw0 sw1 sw2 sw3".split():
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pads = platform.request("eem1_{}".format(signal))
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phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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for i in (1, 2):
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sfp_ctl = platform.request("sfp_ctl", i)
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phy = ttl_simple.Output(sfp_ctl.led)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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self.add_rtio(rtio_channels)
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class Master(MiniSoC, AMPSoC):
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mem_map = {
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"cri_con": 0x10000000,
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@ -542,13 +595,15 @@ def main():
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soc_kasli_args(parser)
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parser.set_defaults(output_dir="artiq_kasli")
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parser.add_argument("-V", "--variant", default="opticlock",
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help="variant: opticlock/master/satellite "
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help="variant: opticlock/sysu/master/satellite "
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"(default: %(default)s)")
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args = parser.parse_args()
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variant = args.variant.lower()
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if variant == "opticlock":
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cls = Opticlock
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elif variant == "sysu":
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cls = SYSU
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elif variant == "master":
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cls = Master
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elif variant == "satellite":
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