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urukul: example additions

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* relax timings for faster spi xfers
* continuous readback test to explore spi speed limit
This commit is contained in:
Robert Jördens 2018-01-22 08:25:12 +00:00 committed by Robert Jordens
parent 5a9035b122
commit a86b28def2
1 changed files with 19 additions and 5 deletions
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24
artiq/examples/master/repository/coredevice_examples/simple/urukul.py
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@ -34,28 +34,42 @@ class UrukulTest(EnvExperiment):
self.urukul_ch2b.init()
self.urukul_ch3b.init()
delay(100*us)
delay(1000*us)
self.urukul_ch0b.set(100*MHz)
self.urukul_ch0b.sw.on()
self.urukul_ch0b.set_att(10.)
delay(100*us)
delay(1000*us)
self.urukul_ch1b.set(10*MHz, 0.5)
self.urukul_ch1b.sw.on()
self.urukul_ch1b.set_att(0.)
delay(100*us)
delay(1000*us)
self.urukul_ch2b.set(400*MHz)
self.urukul_ch2b.sw.on()
self.urukul_ch2b.set_att(0.)
delay(100*us)
delay(1000*us)
self.urukul_ch3b.set(1*MHz)
self.urukul_ch3b.sw.on()
self.urukul_ch3b.set_att(20.)
i = 0
j = 0
while True:
self.urukul_ch0b.set_mu(0x12345678, 0, 0x3fff)
delay(13*us)
self.urukul_ch0b.write32(0x07, i)
self.urukul_cpld.io_update.pulse(10*ns)
k = self.urukul_ch0b.read32(0x07)
delay(100*us)
if k != i:
#print(i)
#print(k)
#if j > 20:
# return
j += 1
#delay(20*ms)
i += 1
while True:
self.urukul_ch0b.sw.pulse(5*ms)