forked from M-Labs/artiq
parent
8b70db5f17
commit
a6d1b030c1
@ -67,7 +67,7 @@ class Core(Module, AutoCSR):
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coarse_ts = Signal(64-glbl_fine_ts_width)
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coarse_ts = Signal(64-glbl_fine_ts_width)
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self.sync.rtio += coarse_ts.eq(coarse_ts + 1)
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self.sync.rtio += coarse_ts.eq(coarse_ts + 1)
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coarse_ts_cdc = GrayCodeTransfer(len(coarse_ts))
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coarse_ts_cdc = GrayCodeTransfer(len(coarse_ts)) # from rtio to sys
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self.submodules += coarse_ts_cdc
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self.submodules += coarse_ts_cdc
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self.comb += [
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self.comb += [
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coarse_ts_cdc.i.eq(coarse_ts),
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coarse_ts_cdc.i.eq(coarse_ts),
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@ -83,7 +83,7 @@ class Core(Module, AutoCSR):
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interface=self.cri)
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interface=self.cri)
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self.submodules += outputs
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self.submodules += outputs
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self.comb += outputs.coarse_timestamp.eq(coarse_ts)
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self.comb += outputs.coarse_timestamp.eq(coarse_ts)
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self.sync += outputs.minimum_coarse_timestamp.eq(coarse_ts + 16)
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self.sync += outputs.minimum_coarse_timestamp.eq(coarse_ts_cdc.o + 16)
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inputs = InputCollector(channels, glbl_fine_ts_width, "async",
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inputs = InputCollector(channels, glbl_fine_ts_width, "async",
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quash_channels=quash_channels,
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quash_channels=quash_channels,
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