forked from M-Labs/artiq
1
0
Fork 0

test: RTIO underflow exception

This commit is contained in:
Sebastien Bourdeauducq 2014-09-25 12:57:52 +08:00
parent 4f26b6281d
commit a6580c3fa2
1 changed files with 24 additions and 4 deletions

View File

@ -2,7 +2,7 @@ import unittest
from artiq.language.core import * from artiq.language.core import *
from artiq.language.units import * from artiq.language.units import *
from artiq.devices import corecom_serial, core, rtio_core from artiq.devices import corecom_serial, core, runtime_exceptions, rtio_core
from artiq.sim import devices as sim_devices from artiq.sim import devices as sim_devices
@ -100,16 +100,36 @@ class _RTIOLoopback(AutoContext):
self.report(self.i.sync()) self.report(self.i.sync())
class _RTIOUnderflow(AutoContext):
parameters = "o"
@kernel
def run(self):
for i in range(10000):
delay(25*ns)
self.o.pulse(25*ns)
class RTIOCase(unittest.TestCase): class RTIOCase(unittest.TestCase):
def test_loopback(self): def test_loopback(self):
npulses = 4 npulses = 4
with corecom_serial.CoreCom() as com: with corecom_serial.CoreCom() as com:
coredev = core.Core(com) coredev = core.Core(com)
lb = _RTIOLoopback( uut = _RTIOLoopback(
core=coredev, core=coredev,
i=rtio_core.RTIOCounter(core=coredev, channel=0), i=rtio_core.RTIOCounter(core=coredev, channel=0),
o=rtio_core.RTIOOut(core=coredev, channel=1), o=rtio_core.RTIOOut(core=coredev, channel=1),
npulses=npulses npulses=npulses
) )
lb.run() uut.run()
self.assertEqual(lb.result, npulses) self.assertEqual(uut.result, npulses)
def test_underflow(self):
with corecom_serial.CoreCom() as com:
coredev = core.Core(com)
uut = _RTIOUnderflow(
core=coredev,
o=rtio_core.RTIOOut(core=coredev, channel=1)
)
with self.assertRaises(runtime_exceptions.RTIOUnderflow):
uut.run()