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kasli: use 125MHz DRTIO freq for testing

This commit is contained in:
Sebastien Bourdeauducq 2018-10-04 10:41:01 +08:00
parent 969a305c5a
commit 9f96b6bcda
1 changed files with 2 additions and 2 deletions
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4
artiq/gateware/targets/kasli.py
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@ -685,7 +685,7 @@ class _MasterBase(MiniSoC, AMPSoC):
}
mem_map.update(MiniSoC.mem_map)
def __init__(self, rtio_clk_freq=150e6, **kwargs):
def __init__(self, rtio_clk_freq=125e6, **kwargs):
MiniSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
@ -834,7 +834,7 @@ class _SatelliteBase(BaseSoC):
}
mem_map.update(BaseSoC.mem_map)
def __init__(self, rtio_clk_freq=150e6, **kwargs):
def __init__(self, rtio_clk_freq=125e6, **kwargs):
BaseSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",