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soc: increase DDS output FIFO sizes

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This commit is contained in:
Sebastien Bourdeauducq 2015-06-21 08:40:10 -06:00
parent b7d976e7db
commit 9f3f9255a2
2 changed files with 6 additions and 2 deletions
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4
soc/targets/artiq_kc705.py
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@ -83,7 +83,9 @@ class NIST_QC1(MiniSoC, AMPSoC):
self.add_constant("DDS_CHANNEL_COUNT", 8)
phy = dds.AD9858(platform.request("dds"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
rtio_channels.append(rtio.Channel.from_phy(phy,
ofifo_depth=512,
ififo_depth=4))
# RTIO core
self.submodules.rtio_crg = _RTIOCRG(platform, self.crg.pll_sys)

4
soc/targets/artiq_pipistrello.py
View File

@ -118,7 +118,9 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
self.add_constant("DDS_CHANNEL_COUNT", 8)
phy = dds.AD9858(platform.request("dds"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
rtio_channels.append(rtio.Channel.from_phy(phy,
ofifo_depth=512,
ififo_depth=4))
# RTIO core
self.submodules.rtio_crg = _RTIOCRG(platform)