forked from M-Labs/artiq
ppro: ignore all async paths
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70916aa0c5
commit
9e726d7dd1
@ -48,11 +48,16 @@ class _RTIOMiniCRG(Module, AutoCSR):
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o_O=self.cd_rtio.clk)
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platform.add_platform_command("""
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NET "{rtio_clk}" TNM_NET = "GRPrtio_clk";
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NET "{int_clk}" TNM_NET = "GRPint_clk";
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NET "{ext_clk}" TNM_NET = "GRPext_clk";
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NET "sys_clk" TNM_NET = "GRPsys_clk";
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TIMESPEC "TSfix_ise1" = FROM "GRPrtio_clk" TO "GRPsys_clk" TIG;
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TIMESPEC "TSfix_ise2" = FROM "GRPsys_clk" TO "GRPrtio_clk" TIG;
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""", rtio_clk=rtio_internal_clk)
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TIMESPEC "TSfix_ise1" = FROM "GRPint_clk" TO "GRPsys_clk" TIG;
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TIMESPEC "TSfix_ise2" = FROM "GRPsys_clk" TO "GRPint_clk" TIG;
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TIMESPEC "TSfix_ise3" = FROM "GRPext_clk" TO "GRPsys_clk" TIG;
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TIMESPEC "TSfix_ise4" = FROM "GRPsys_clk" TO "GRPext_clk" TIG;
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TIMESPEC "TSfix_ise5" = FROM "GRPext_clk" TO "GRPint_clk" TIG;
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TIMESPEC "TSfix_ise6" = FROM "GRPint_clk" TO "GRPext_clk" TIG;
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""", int_clk=rtio_internal_clk, ext_clk=rtio_external_clk)
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class UP(BaseSoC):
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