forked from M-Labs/artiq
sayma: use SERDES RTIO TTL
This is not enabled on the standalone design as it breaks timing.
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@ -31,7 +31,7 @@ from artiq.gateware.amp import AMPSoC
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from artiq.gateware import serwb
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from artiq.gateware import remote_csr
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_simple, sawg
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_ultrascale, sawg
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from artiq.gateware.drtio.transceiver import gth_ultrascale
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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@ -126,6 +126,53 @@ class AD9154NoSAWG(Module, AutoCSR):
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for i in range(len(conv) // len(ramp))))
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class _RTIOClockMultiplier(Module):
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def __init__(self, platform, rtio_clk_freq):
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self.clock_domains.cd_rtio_serdes = ClockDomain()
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self.clock_domains.cd_rtiox4_serdes = ClockDomain(reset_less=True)
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# See "Global Clock Network Deskew Using Two BUFGs" in ug572.
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# See also AR#67885.
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clkfbout = Signal()
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clkfbin = Signal()
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rtio_clk = Signal()
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rtiox4_clk = Signal()
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self.specials += [
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Instance("MMCME2_BASE",
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p_CLKIN1_PERIOD=1e9/rtio_clk_freq,
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i_CLKIN1=ClockSignal("rtio"),
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i_RST=ResetSignal("rtio"),
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p_CLKFBOUT_MULT_F=8.0, p_DIVCLK_DIVIDE=1,
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o_CLKFBOUT=clkfbout, i_CLKFBIN=clkfbin,
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p_CLKOUT1_DIVIDE=8, o_CLKOUT1=rtio_clk,
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p_CLKOUT2_DIVIDE=2, o_CLKOUT2=rtiox4_clk,
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),
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Instance("BUFG", name="rtioserdes_bufg_fb",
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i_I=clkfbout, o_O=clkfbin),
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Instance("BUFG", name="rtioserdes_bufg_div",
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i_I=rtio_clk, o_O=self.cd_rtio_serdes.clk),
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Instance("BUFG", name="rtioserdes_bufg",
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i_I=rtiox4_clk, o_O=self.cd_rtiox4_serdes.clk)
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]
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self.comb += self.cd_rtio_serdes.rst.eq(ResetSignal("rio_phy"))
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platform.add_platform_command(
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"set_property CLOCK_DELAY_GROUP RTIOSERDES_BALANCE [get_nets -of [get_pins rtioserdes_bufg_fb/O]]")
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platform.add_platform_command(
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"set_property CLOCK_DELAY_GROUP RTIOSERDES_BALANCE [get_nets -of [get_pins rtioserdes_bufg_div/O]]")
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platform.add_platform_command(
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"set_property CLOCK_DELAY_GROUP RTIOSERDES_BALANCE [get_nets -of [get_pins rtioserdes_bufg/O]]")
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platform.add_platform_command(
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"set_property USER_CLOCK_ROOT X2Y1 [get_nets -of [get_pins rtioserdes_bufg_fb/O]]")
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platform.add_platform_command(
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"set_property USER_CLOCK_ROOT X2Y1 [get_nets -of [get_pins rtioserdes_bufg_div/O]]")
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platform.add_platform_command(
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"set_property USER_CLOCK_ROOT X2Y1 [get_nets -of [get_pins rtioserdes_bufg/O]]")
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class Standalone(MiniSoC, AMPSoC):
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mem_map = {
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"cri_con": 0x10000000,
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@ -341,6 +388,7 @@ class Master(MiniSoC, AMPSoC):
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, gth.rxoutclk)
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self.submodules.rtio_clkmul = _RTIOClockMultiplier(platform, rtio_clk_freq)
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rtio_channels = []
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for i in range(4):
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phy = ttl_simple.Output(platform.request("user_led", i))
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@ -348,12 +396,12 @@ class Master(MiniSoC, AMPSoC):
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 0)
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self.comb += sma_io.direction.eq(1)
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phy = ttl_simple.Output(sma_io.level)
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phy = ttl_serdes_ultrascale.Output_8X(sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 1)
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self.comb += sma_io.direction.eq(0)
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phy = ttl_simple.InOut(sma_io.level)
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phy = ttl_serdes_ultrascale.InOut_8X(sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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@ -397,6 +445,7 @@ class Satellite(BaseSoC):
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self.submodules += Microscope(platform.request("serial", 1),
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self.clk_freq)
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self.submodules.rtio_clkmul = _RTIOClockMultiplier(platform, rtio_clk_freq)
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rtio_channels = []
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for i in range(4):
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phy = ttl_simple.Output(platform.request("user_led", i))
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@ -404,12 +453,12 @@ class Satellite(BaseSoC):
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 0)
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self.comb += sma_io.direction.eq(1)
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phy = ttl_simple.Output(sma_io.level)
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phy = ttl_serdes_ultrascale.Output_8X(sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 1)
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self.comb += sma_io.direction.eq(0)
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phy = ttl_simple.InOut(sma_io.level)
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phy = ttl_serdes_ultrascale.InOut_8X(sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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