forked from M-Labs/artiq
rtio/sed: support negative latency compensation
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@ -81,7 +81,8 @@ class LaneDistributor(Module):
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self.comb += latency_compensation_port.adr.eq(self.cri.chan_sel[:16])
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# cycle #2, write
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compensation = latency_compensation_port.dat_r
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compensation = Signal((14, True))
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self.comb += compensation.eq(latency_compensation_port.dat_r)
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timestamp_above_min = Signal()
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timestamp_above_laneA_min = Signal()
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timestamp_above_laneB_min = Signal()
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