occheung/artiq
1
0
Fork 0
forked from M-Labs/artiq
Code Pull Requests Activity

kasli: add second urukul, make clk_sel drive optional

Browse Source
This commit is contained in:
Robert Jördens 2018-03-05 18:07:04 +01:00
parent 07de7af86a
commit 956098c213
1 changed files with 6 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
artiq/gateware/targets/kasli.py
View File

@ -252,9 +252,14 @@ class Opticlock(_StandaloneBase):
platform.add_extension(_dio("eem2"))
platform.add_extension(_novogorny("eem3"))
platform.add_extension(_urukul("eem5", "eem4"))
platform.add_extension(_urukul("eem6"))
# platform.add_extension(_zotino("eem7"))
# EEM clock fan-out from Si5324, not MMCX
self.comb += platform.request("clk_sel").eq(1)
try:
self.comb += platform.request("clk_sel").eq(1)
except ConstraintError:
pass
rtio_channels = []
for i in range(24):