pipistrello: set RTIO_SPI_CHANNEL

2016-02-29 00:37:00 +01:00 · 2016-02-29 00:37:00 +01:00 · 8d7e92ebae
parent 9a881aa430
commit 8d7e92ebae
1 changed files with 1 additions and 0 deletions
--- a/artiq/gateware/targets/pipistrello.py
+++ b/artiq/gateware/targets/pipistrello.py
@ -200,6 +200,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
        spi_pins.cs_n = pmod.d[3:]
        phy = spi.SPIMaster(spi_pins)
        self.submodules += phy
+        self.config["RTIO_SPI_CHANNEL"] = len(rtio_channels)
        rtio_channels.append(rtio.Channel.from_phy(
            phy, ofifo_depth=4, ififo_depth=4))