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rtio/sed: fix sequence number width computation

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This commit is contained in:
Sebastien Bourdeauducq 2017-09-13 22:11:41 +08:00
parent a92a955d1e
commit 8cfe2ec53a
1 changed files with 3 additions and 1 deletions
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4
artiq/gateware/rtio/sed/lane_distributor.py
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@ -25,7 +25,9 @@ class LaneDistributor(Module):
if lane_count & (lane_count - 1):
raise NotImplementedError("lane count must be a power of 2")
seqn_width = 4*bits_for(lane_count*fifo_size-1)
# There must be a unique sequence number for every possible event in every FIFO.
# Plus 2 bits to detect and handle wraparounds.
seqn_width = bits_for(lane_count*fifo_size-1) + 2
self.cri = cri.Interface()
self.minimum_coarse_timestamp = Signal(64-fine_ts_width)