forked from M-Labs/artiq
drtio: report busy errors
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@ -112,6 +112,8 @@ class IOS(Module):
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if fine_ts_width:
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self.sync.rio += interface.fine_ts.eq(fifo_out.timestamp[:fine_ts_width])
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self.sync.rio += If(interface.stb & interface.busy, self.busy.eq(1))
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def add_input(self, n, channel):
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rt_packet = self.rt_packet
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