forked from M-Labs/artiq
add Metlino support
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cfe1f56f73
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874542f33f
@ -231,6 +231,10 @@ fn startup_ethernet() {
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{
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hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x11]);
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}
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#[cfg(soc_platform = "metlino")]
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{
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hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x19]);
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}
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#[cfg(soc_platform = "kc705")]
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{
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hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x01]);
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@ -254,6 +258,10 @@ fn startup_ethernet() {
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{
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protocol_addr = IpAddress::v4(192, 168, 1, 60);
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}
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#[cfg(soc_platform = "metlino")]
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{
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protocol_addr = IpAddress::v4(192, 168, 1, 65);
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}
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#[cfg(soc_platform = "kc705")]
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{
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protocol_addr = IpAddress::v4(192, 168, 1, 50);
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177
artiq/gateware/targets/metlino.py
Executable file
177
artiq/gateware/targets/metlino.py
Executable file
@ -0,0 +1,177 @@
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#!/usr/bin/env python3
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import argparse
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from migen import *
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from misoc.cores import gpio
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from misoc.integration.builder import builder_args, builder_argdict
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from misoc.interconnect.csr import *
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from misoc.targets.metlino import *
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from artiq.gateware.amp import AMPSoC
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from artiq.gateware import eem
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from artiq.gateware import fmcdio_vhdci_eem
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_ultrascale
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from artiq.gateware.drtio.transceiver import gth_ultrascale
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from artiq.gateware.drtio import *
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from artiq.build_soc import *
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def workaround_us_lvds_tristate(platform):
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# Those shoddy Kintex Ultrascale FPGAs take almost a microsecond to change the direction of a
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# LVDS I/O buffer. The application has to cope with it and this cannot be handled at static
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# timing analysis. Disable the latter for IOBUFDS.
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# See:
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# https://forums.xilinx.com/t5/Timing-Analysis/Delay-890-ns-in-OBUFTDS-in-Kintex-UltraScale/td-p/868364
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platform.add_platform_command(
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"set_false_path -through [get_pins -filter {{REF_PIN_NAME == T}} -of [get_cells -filter {{REF_NAME == IOBUFDS}}]]")
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class Master(MiniSoC, AMPSoC):
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mem_map = {
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"cri_con": 0x10000000,
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"rtio": 0x11000000,
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"rtio_dma": 0x12000000,
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"drtioaux": 0x14000000,
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"mailbox": 0x70000000
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, **kwargs):
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MiniSoC.__init__(self,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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ethmac_nrxslots=4,
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ethmac_ntxslots=4,
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**kwargs)
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AMPSoC.__init__(self)
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add_identifier(self)
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platform = self.platform
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rtio_clk_freq = 150e6
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
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self.csr_devices.append("si5324_rst_n")
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_SI5324"] = None
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self.config["SI5324_AS_SYNTHESIZER"] = None
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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self.submodules.drtio_transceiver = gth_ultrascale.GTH(
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clock_pads=platform.request("cdr_clk_clean", 0),
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data_pads=[platform.request("mch_fabric_d", i) for i in range(12)],
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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drtio_csr_group = []
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drtioaux_csr_group = []
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drtioaux_memory_group = []
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drtio_cri = []
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for i in range(len(self.drtio_transceiver.channels)):
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core_name = "drtio" + str(i)
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coreaux_name = "drtioaux" + str(i)
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memory_name = "drtioaux" + str(i) + "_mem"
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drtio_csr_group.append(core_name)
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drtioaux_csr_group.append(coreaux_name)
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drtioaux_memory_group.append(memory_name)
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cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
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core = cdr(DRTIOMaster(self.rtio_tsc, self.drtio_transceiver.channels[i]))
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setattr(self.submodules, core_name, core)
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drtio_cri.append(core.cri)
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self.csr_devices.append(core_name)
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coreaux = cdr(DRTIOAuxController(core.link_layer))
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setattr(self.submodules, coreaux_name, coreaux)
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self.csr_devices.append(coreaux_name)
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memory_address = self.mem_map["drtioaux"] + 0x800*i
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self.add_wb_slave(memory_address, 0x800,
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coreaux.bus)
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self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
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self.config["HAS_DRTIO"] = None
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self.config["HAS_DRTIO_ROUTING"] = None
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self.add_csr_group("drtio", drtio_csr_group)
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self.add_csr_group("drtioaux", drtioaux_csr_group)
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self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
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rtio_clk_period = 1e9/rtio_clk_freq
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gth0 = self.drtio_transceiver.gths[0]
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platform.add_period_constraint(gth0.txoutclk, rtio_clk_period/2)
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platform.add_period_constraint(gth0.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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gth0.txoutclk, gth0.rxoutclk)
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for gth in self.drtio_transceiver.gths[1:]:
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platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, gth0.txoutclk, gth.rxoutclk)
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self.rtio_channels = rtio_channels = []
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for i in range(4):
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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#platform.add_extension(fmcdio_vhdci_eem.io)
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#platform.add_connectors(fmcdio_vhdci_eem.connectors)
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#fmcdio_dirctl = platform.request("fmcdio_dirctl")
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#for s in fmcdio_dirctl.clk, fmcdio_dirctl.ser, fmcdio_dirctl.latch:
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# phy = ttl_simple.Output(s)
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# self.submodules += phy
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# rtio_channels.append(rtio.Channel.from_phy(phy))
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#eem.DIO.add_std(self, 2, ttl_simple.Output, ttl_simple.Output,
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# iostandard="LVDS")
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#eem.Urukul.add_std(self, 1, 0, ttl_simple.Output,
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# iostandard="LVDS")
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#eem.Zotino.add_std(self, 3, ttl_simple.Output,
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# iostandard="LVDS")
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#workaround_us_lvds_tristate(platform)
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
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self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
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rtio.DMA(self.get_native_sdram_if()))
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self.register_kernel_cpu_csrdevice("rtio")
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self.register_kernel_cpu_csrdevice("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri] + drtio_cri,
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enable_routing=True)
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self.register_kernel_cpu_csrdevice("cri_con")
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self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
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self.csr_devices.append("routing_table")
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def main():
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parser = argparse.ArgumentParser(
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description="Metlino gateware and firmware builder")
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builder_args(parser)
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soc_sdram_args(parser)
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parser.set_defaults(output_dir="artiq_metlino")
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args = parser.parse_args()
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soc = Master(**soc_sdram_argdict(args))
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build_artiq_soc(soc, builder_argdict(args))
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if __name__ == "__main__":
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main()
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