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ad9910: fix pll_en doc

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Sebastien Bourdeauducq 2023-01-15 12:30:08 +08:00
parent 9e8167e1fa
commit 78daace19a
1 changed files with 1 additions and 1 deletions
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artiq/coredevice/ad9910.py
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@ -127,7 +127,7 @@ class AD9910:
f_ref/clk_div*pll_n where f_ref is the reference frequency and
clk_div is the reference clock divider (both set in the parent
Urukul CPLD instance).
:param pll_en: PLL enable bit, set to 0 to bypass PLL (default: 1).
:param pll_en: PLL enable bit, set to False to bypass PLL (default: True).
Note that when bypassing the PLL the red front panel LED may remain on.
:param pll_cp: DDS PLL charge pump setting.
:param pll_vco: DDS PLL VCO range selection.