forked from M-Labs/artiq
coredevice/test: add unittests for exceptions
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@ -53,6 +53,9 @@ def rtio_get_destination_status(linkno: TInt32) -> TBool:
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def rtio_get_counter() -> TInt64:
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raise NotImplementedError("syscall not simulated")
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@syscall
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def raise_exception(id: TInt32) -> TNone:
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raise NotImplementedError("syscall not simulated")
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def get_target_cls(target):
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if target == "rv32g":
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@ -0,0 +1,59 @@
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import unittest
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import artiq.coredevice.exceptions as exceptions
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from artiq.experiment import *
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from artiq.test.hardware_testbench import ExperimentCase
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from artiq.compiler.embedding import EmbeddingMap
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from artiq.coredevice.core import raise_exception
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"""
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Test sync in exceptions raised between host and kernel
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Check artiq.compiler.embedding and artiq.frontend.ksupport.eh_artiq
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Considers the following two cases:
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1) Exception raised on kernel and passed to host
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2) Exception raised in host function called from kernel
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Ensures integirty of exceptions is maintained as it passes between kernel and host
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"""
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exception_names = EmbeddingMap().str_reverse_map
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class _TestExceptionSync(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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@rpc
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def _raise_exception_host(self, id):
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exn = exception_names[id].split('.')[-1].split(':')[-1]
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exn = getattr(exceptions, exn)
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raise exn
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@kernel
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def raise_exception_host(self, id):
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self._raise_exception_host(id)
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@kernel
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def raise_exception_kernel(self, id):
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raise_exception(id)
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class ExceptionTest(ExperimentCase):
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def test_raise_exceptions_kernel(self):
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exp = self.create(_TestExceptionSync)
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for id, name in list(exception_names.items())[::-1]:
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name = name.split('.')[-1].split(':')[-1]
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with self.assertRaises(getattr(exceptions, name)) as ctx:
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exp.raise_exception_kernel(id)
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self.assertEqual(str(ctx.exception).strip("'"), name)
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def test_raise_exceptions_host(self):
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exp = self.create(_TestExceptionSync)
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for id, name in exception_names.items():
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name = name.split('.')[-1].split(':')[-1]
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with self.assertRaises(getattr(exceptions, name)) as ctx:
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exp.raise_exception_host(id)
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