forked from M-Labs/artiq
kasli/sysu: add comments
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@ -549,6 +549,7 @@ class SYSU(_StandaloneBase):
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# EEM clock fan-out from Si5324, not MMCX
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self.comb += platform.request("clk_sel").eq(1)
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# EEM2-6: TTL
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rtio_channels = []
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for i in range(40):
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eem_offset, port = divmod(i, 8)
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@ -557,6 +558,7 @@ class SYSU(_StandaloneBase):
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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# EEM0, EEM1: Urukul
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phy = spi2.SPIMaster(self.platform.request("eem1_spi_p"),
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self.platform.request("eem1_spi_n"))
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self.submodules += phy
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