forked from M-Labs/artiq
fix old line that I forgot
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5df766e6da
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@ -1073,9 +1073,7 @@ class PhaserChannel:
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data = 1
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if hold == 1:
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data = data | (1 << 1)
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if bypass:
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hold = 1
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data = (profile << 2) | (hold << 1) | (bypass << 0)
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data = data | (profile << 2)
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self.phaser.write8(addr, data)
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@kernel
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