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sayma: output a ramp in the absence of SAWG channels

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This commit is contained in:
Robert Jördens 2017-12-31 12:18:37 +01:00
parent a371b25525
commit 745e695b09
1 changed files with 30 additions and 13 deletions
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21
artiq/gateware/targets/sayma_amc_standalone.py
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@ -99,6 +99,19 @@ class AD9154(Module, AutoCSR):
self.sync.jesd += conv.eq(Cat(ch.o))
class AD9154NoSAWG(Module, AutoCSR):
def __init__(self, platform, sys_crg, jesd_crg, dac):
self.submodules.jesd = AD9154JESD(platform, sys_crg, jesd_crg, dac)
self.sawgs = []
for i, conv in enumerate(self.jesd.core.sink.flatten()):
ramp = Signal(16)
self.sync += ramp.eq(ramp + (1 << 9 + i))
self.comb += conv.eq(Cat(ramp
for i in range(len(conv) // len(ramp))))
class Standalone(MiniSoC, AMPSoC):
mem_map = {
"cri_con": 0x10000000,
@ -177,9 +190,13 @@ class Standalone(MiniSoC, AMPSoC):
rtio_channels.append(rtio.Channel.from_phy(phy))
if with_sawg:
cls = AD9154
else:
cls = AD9154NoSAWG
self.submodules.ad9154_crg = AD9154CRG(platform)
self.submodules.ad9154_0 = AD9154(platform, self.crg, self.ad9154_crg, 0)
self.submodules.ad9154_1 = AD9154(platform, self.crg, self.ad9154_crg, 1)
self.submodules.ad9154_0 = cls(platform, self.crg, self.ad9154_crg, 0)
self.submodules.ad9154_1 = cls(platform, self.crg, self.ad9154_crg, 1)
self.csr_devices.append("ad9154_crg")
self.csr_devices.append("ad9154_0")
self.csr_devices.append("ad9154_1")