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sayma: rtio clock is jesd fabric clock

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This commit is contained in:
Robert Jördens 2018-01-16 18:19:04 +01:00
parent 3eb882b6b7
commit 7405006668
1 changed files with 2 additions and 2 deletions
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4
artiq/gateware/targets/sayma_amc_standalone.py
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@ -220,8 +220,8 @@ class Standalone(MiniSoC, AMPSoC):
self.clock_domains.cd_rtio = ClockDomain()
self.comb += [
self.cd_rtio.clk.eq(ClockSignal()),
self.cd_rtio.rst.eq(ResetSignal())
self.cd_rtio.clk.eq(ClockSignal("jesd")),
self.cd_rtio.rst.eq(ResetSignal("jesd"))
]
self.submodules.rtio_core = rtio.Core(rtio_channels)
self.csr_devices.append("rtio_core")