forked from M-Labs/artiq
ad9910: port imports and type annotations to NAC3
This commit is contained in:
parent
2720bfa398
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70531ae1e2
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@ -1,9 +1,7 @@
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from numpy import int32, int64
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from artiq.language.core import (
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kernel, delay, portable, delay_mu, now_mu, at_mu)
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from artiq.language.core import kernel, portable
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from artiq.language.units import us, ms
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from artiq.language.types import TBool, TInt32, TInt64, TFloat, TList, TTuple
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from artiq.coredevice import spi2 as spi
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from artiq.coredevice import urukul
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@ -187,7 +185,7 @@ class AD9910:
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self.phase_mode = PHASE_MODE_CONTINUOUS
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@kernel
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def set_phase_mode(self, phase_mode: TInt32):
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def set_phase_mode(self, phase_mode: int32):
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r"""Set the default phase mode.
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for future calls to :meth:`set` and
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@ -232,7 +230,7 @@ class AD9910:
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self.phase_mode = phase_mode
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@kernel
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def write16(self, addr: TInt32, data: TInt32):
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def write16(self, addr: int32, data: int32):
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"""Write to 16 bit register.
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:param addr: Register address
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@ -243,7 +241,7 @@ class AD9910:
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self.bus.write((addr << 24) | ((data & 0xffff) << 8))
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@kernel
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def write32(self, addr: TInt32, data: TInt32):
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def write32(self, addr: int32, data: int32):
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"""Write to 32 bit register.
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:param addr: Register address
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@ -257,7 +255,7 @@ class AD9910:
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self.bus.write(data)
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@kernel
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def read16(self, addr: TInt32) -> TInt32:
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def read16(self, addr: int32) -> int32:
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"""Read from 16 bit register.
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:param addr: Register address
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@ -272,7 +270,7 @@ class AD9910:
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return self.bus.read()
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@kernel
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def read32(self, addr: TInt32) -> TInt32:
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def read32(self, addr: int32) -> int32:
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"""Read from 32 bit register.
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:param addr: Register address
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@ -287,7 +285,7 @@ class AD9910:
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return self.bus.read()
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@kernel
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def read64(self, addr: TInt32) -> TInt64:
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def read64(self, addr: int32) -> int64:
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"""Read from 64 bit register.
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:param addr: Register address
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@ -310,7 +308,7 @@ class AD9910:
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return (int64(hi) << 32) | lo
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@kernel
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def write64(self, addr: TInt32, data_high: TInt32, data_low: TInt32):
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def write64(self, addr: int32, data_high: int32, data_low: int32):
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"""Write to 64 bit register.
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:param addr: Register address
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@ -328,7 +326,7 @@ class AD9910:
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self.bus.write(data_low)
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@kernel
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def write_ram(self, data: TList(TInt32)):
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def write_ram(self, data: list[int32]):
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"""Write data to RAM.
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The profile to write to and the step, start, and end address
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@ -349,7 +347,7 @@ class AD9910:
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self.bus.write(data[len(data) - 1])
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@kernel
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def read_ram(self, data: TList(TInt32)):
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def read_ram(self, data: list[int32]):
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"""Read data from RAM.
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The profile to read from and the step, start, and end address
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@ -379,17 +377,17 @@ class AD9910:
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@kernel
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def set_cfr1(self,
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power_down: TInt32 = 0b0000,
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phase_autoclear: TInt32 = 0,
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drg_load_lrr: TInt32 = 0,
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drg_autoclear: TInt32 = 0,
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phase_clear: TInt32 = 0,
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internal_profile: TInt32 = 0,
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ram_destination: TInt32 = 0,
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ram_enable: TInt32 = 0,
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manual_osk_external: TInt32 = 0,
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osk_enable: TInt32 = 0,
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select_auto_osk: TInt32 = 0):
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power_down: int32 = 0b0000,
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phase_autoclear: int32 = 0,
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drg_load_lrr: int32 = 0,
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drg_autoclear: int32 = 0,
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phase_clear: int32 = 0,
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internal_profile: int32 = 0,
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ram_destination: int32 = 0,
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ram_enable: int32 = 0,
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manual_osk_external: int32 = 0,
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osk_enable: int32 = 0,
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select_auto_osk: int32 = 0):
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"""Set CFR1. See the AD9910 datasheet for parameter meanings.
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This method does not pulse IO_UPDATE.
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@ -424,11 +422,11 @@ class AD9910:
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@kernel
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def set_cfr2(self,
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asf_profile_enable: TInt32 = 1,
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drg_enable: TInt32 = 0,
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effective_ftw: TInt32 = 1,
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sync_validation_disable: TInt32 = 0,
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matched_latency_enable: TInt32 = 0):
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asf_profile_enable: int32 = 1,
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drg_enable: int32 = 0,
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effective_ftw: int32 = 1,
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sync_validation_disable: int32 = 0,
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matched_latency_enable: int32 = 0):
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"""Set CFR2. See the AD9910 datasheet for parameter meanings.
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This method does not pulse IO_UPDATE.
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@ -452,7 +450,7 @@ class AD9910:
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(sync_validation_disable << 5))
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@kernel
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def init(self, blind: TBool = False):
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def init(self, blind: bool = False):
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"""Initialize and configure the DDS.
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Sets up SPI mode, confirms chip presence, powers down unused blocks,
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@ -511,7 +509,7 @@ class AD9910:
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delay(1 * ms)
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@kernel
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def power_down(self, bits: TInt32 = 0b1111):
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def power_down(self, bits: int32 = 0b1111):
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"""Power down DDS.
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:param bits: Power down bits, see datasheet
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@ -520,11 +518,11 @@ class AD9910:
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self.cpld.io_update.pulse(1 * us)
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@kernel
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def set_mu(self, ftw: TInt32 = 0, pow_: TInt32 = 0, asf: TInt32 = 0x3fff,
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phase_mode: TInt32 = _PHASE_MODE_DEFAULT,
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ref_time_mu: TInt64 = int64(-1),
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profile: TInt32 = DEFAULT_PROFILE,
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ram_destination: TInt32 = -1) -> TInt32:
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def set_mu(self, ftw: int32 = 0, pow_: int32 = 0, asf: int32 = 0x3fff,
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phase_mode: int32 = _PHASE_MODE_DEFAULT,
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ref_time_mu: int64 = int64(-1),
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profile: int32 = DEFAULT_PROFILE,
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ram_destination: int32 = -1) -> int32:
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"""Set DDS data in machine units.
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This uses machine units (FTW, POW, ASF). The frequency tuning word
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@ -593,8 +591,8 @@ class AD9910:
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return pow_
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@kernel
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def get_mu(self, profile: TInt32 = DEFAULT_PROFILE
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) -> TTuple([TInt32, TInt32, TInt32]):
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def get_mu(self, profile: int32 = DEFAULT_PROFILE
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) -> tuple[int32, int32, int32]:
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"""Get the frequency tuning word, phase offset word,
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and amplitude scale factor.
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@ -613,10 +611,10 @@ class AD9910:
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return ftw, pow_, asf
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@kernel
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def set_profile_ram(self, start: TInt32, end: TInt32, step: TInt32 = 1,
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profile: TInt32 = _DEFAULT_PROFILE_RAM,
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nodwell_high: TInt32 = 0, zero_crossing: TInt32 = 0,
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mode: TInt32 = 1):
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def set_profile_ram(self, start: int32, end: int32, step: int32 = 1,
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profile: int32 = _DEFAULT_PROFILE_RAM,
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nodwell_high: int32 = 0, zero_crossing: int32 = 0,
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mode: int32 = 1):
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"""Set the RAM profile settings.
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:param start: Profile start address in RAM.
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@ -640,7 +638,7 @@ class AD9910:
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self.write64(_AD9910_REG_PROFILE0 + profile, hi, lo)
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@kernel
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def set_ftw(self, ftw: TInt32):
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def set_ftw(self, ftw: int32):
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"""Set the value stored to the AD9910's frequency tuning word (FTW)
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register.
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@ -649,7 +647,7 @@ class AD9910:
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self.write32(_AD9910_REG_FTW, ftw)
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@kernel
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def set_asf(self, asf: TInt32):
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def set_asf(self, asf: int32):
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"""Set the value stored to the AD9910's amplitude scale factor (ASF)
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register.
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@ -658,7 +656,7 @@ class AD9910:
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self.write32(_AD9910_REG_ASF, asf << 2)
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@kernel
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def set_pow(self, pow_: TInt32):
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def set_pow(self, pow_: int32):
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"""Set the value stored to the AD9910's phase offset word (POW)
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register.
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@ -667,7 +665,7 @@ class AD9910:
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self.write16(_AD9910_REG_POW, pow_)
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@kernel
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def get_ftw(self) -> TInt32:
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def get_ftw(self) -> int32:
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"""Get the value stored to the AD9910's frequency tuning word (FTW)
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register.
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@ -676,7 +674,7 @@ class AD9910:
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return self.read32(_AD9910_REG_FTW)
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@kernel
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def get_asf(self) -> TInt32:
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def get_asf(self) -> int32:
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"""Get the value stored to the AD9910's amplitude scale factor (ASF)
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register.
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@ -685,7 +683,7 @@ class AD9910:
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return self.read32(_AD9910_REG_ASF) >> 2
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@kernel
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def get_pow(self) -> TInt32:
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def get_pow(self) -> int32:
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"""Get the value stored to the AD9910's phase offset word (POW)
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register.
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@ -693,34 +691,34 @@ class AD9910:
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"""
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return self.read16(_AD9910_REG_POW)
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@portable(flags={"fast-math"})
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def frequency_to_ftw(self, frequency: TFloat) -> TInt32:
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@portable
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def frequency_to_ftw(self, frequency: float) -> int32:
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"""Return the 32-bit frequency tuning word corresponding to the given
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frequency.
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"""
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return int32(round(self.ftw_per_hz * frequency))
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@portable(flags={"fast-math"})
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def ftw_to_frequency(self, ftw: TInt32) -> TFloat:
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@portable
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def ftw_to_frequency(self, ftw: int32) -> float:
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"""Return the frequency corresponding to the given frequency tuning
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word.
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"""
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return ftw / self.ftw_per_hz
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@portable(flags={"fast-math"})
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def turns_to_pow(self, turns: TFloat) -> TInt32:
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@portable
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def turns_to_pow(self, turns: float) -> int32:
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"""Return the 16-bit phase offset word corresponding to the given phase
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in turns."""
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return int32(round(turns * 0x10000)) & int32(0xffff)
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@portable(flags={"fast-math"})
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def pow_to_turns(self, pow_: TInt32) -> TFloat:
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@portable
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def pow_to_turns(self, pow_: int32) -> float:
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"""Return the phase in turns corresponding to a given phase offset
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word."""
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return pow_ / 0x10000
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@portable(flags={"fast-math"})
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def amplitude_to_asf(self, amplitude: TFloat) -> TInt32:
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@portable
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def amplitude_to_asf(self, amplitude: float) -> int32:
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"""Return 14-bit amplitude scale factor corresponding to given
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fractional amplitude."""
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code = int32(round(amplitude * 0x3fff))
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@ -728,14 +726,14 @@ class AD9910:
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raise ValueError("Invalid AD9910 fractional amplitude!")
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return code
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@portable(flags={"fast-math"})
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def asf_to_amplitude(self, asf: TInt32) -> TFloat:
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@portable
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def asf_to_amplitude(self, asf: int32) -> float:
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"""Return amplitude as a fraction of full scale corresponding to given
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amplitude scale factor."""
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return asf / float(0x3fff)
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@portable(flags={"fast-math"})
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def frequency_to_ram(self, frequency: TList(TFloat), ram: TList(TInt32)):
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@portable
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def frequency_to_ram(self, frequency: list[float], ram: list[int32]):
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"""Convert frequency values to RAM profile data.
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To be used with :const:`RAM_DEST_FTW`.
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@ -747,8 +745,8 @@ class AD9910:
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for i in range(len(ram)):
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ram[i] = self.frequency_to_ftw(frequency[i])
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@portable(flags={"fast-math"})
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def turns_to_ram(self, turns: TList(TFloat), ram: TList(TInt32)):
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@portable
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def turns_to_ram(self, turns: list[float], ram: list[int32]):
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"""Convert phase values to RAM profile data.
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To be used with :const:`RAM_DEST_POW`.
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@ -760,8 +758,8 @@ class AD9910:
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for i in range(len(ram)):
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ram[i] = self.turns_to_pow(turns[i]) << 16
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@portable(flags={"fast-math"})
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def amplitude_to_ram(self, amplitude: TList(TFloat), ram: TList(TInt32)):
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@portable
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def amplitude_to_ram(self, amplitude: list[float], ram: list[int32]):
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"""Convert amplitude values to RAM profile data.
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To be used with :const:`RAM_DEST_ASF`.
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@ -773,9 +771,9 @@ class AD9910:
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for i in range(len(ram)):
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ram[i] = self.amplitude_to_asf(amplitude[i]) << 18
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@portable(flags={"fast-math"})
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def turns_amplitude_to_ram(self, turns: TList(TFloat),
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amplitude: TList(TFloat), ram: TList(TInt32)):
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@portable
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def turns_amplitude_to_ram(self, turns: list[float],
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amplitude: list[float], ram: list[int32]):
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"""Convert phase and amplitude values to RAM profile data.
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To be used with :const:`RAM_DEST_POWASF`.
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@ -790,7 +788,7 @@ class AD9910:
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self.amplitude_to_asf(amplitude[i]) << 2)
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@kernel
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def set_frequency(self, frequency: TFloat):
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def set_frequency(self, frequency: float):
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"""Set the value stored to the AD9910's frequency tuning word (FTW)
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register.
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@ -799,7 +797,7 @@ class AD9910:
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self.set_ftw(self.frequency_to_ftw(frequency))
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@kernel
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def set_amplitude(self, amplitude: TFloat):
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def set_amplitude(self, amplitude: float):
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"""Set the value stored to the AD9910's amplitude scale factor (ASF)
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register.
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@ -808,7 +806,7 @@ class AD9910:
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self.set_asf(self.amplitude_to_asf(amplitude))
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@kernel
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def set_phase(self, turns: TFloat):
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def set_phase(self, turns: float):
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"""Set the value stored to the AD9910's phase offset word (POW)
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register.
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@ -817,7 +815,7 @@ class AD9910:
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self.set_pow(self.turns_to_pow(turns))
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@kernel
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def get_frequency(self) -> TFloat:
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def get_frequency(self) -> float:
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"""Get the value stored to the AD9910's frequency tuning word (FTW)
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register.
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@ -826,7 +824,7 @@ class AD9910:
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return self.ftw_to_frequency(self.get_ftw())
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@kernel
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def get_amplitude(self) -> TFloat:
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def get_amplitude(self) -> float:
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"""Get the value stored to the AD9910's amplitude scale factor (ASF)
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register.
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@ -835,7 +833,7 @@ class AD9910:
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return self.asf_to_amplitude(self.get_asf())
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@kernel
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def get_phase(self) -> TFloat:
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def get_phase(self) -> float:
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"""Get the value stored to the AD9910's phase offset word (POW)
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register.
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@ -844,10 +842,10 @@ class AD9910:
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return self.pow_to_turns(self.get_pow())
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@kernel
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def set(self, frequency: TFloat = 0.0, phase: TFloat = 0.0,
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amplitude: TFloat = 1.0, phase_mode: TInt32 = _PHASE_MODE_DEFAULT,
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ref_time_mu: TInt64 = int64(-1), profile: TInt32 = DEFAULT_PROFILE,
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ram_destination: TInt32 = -1) -> TFloat:
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def set(self, frequency: float = 0.0, phase: float = 0.0,
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amplitude: float = 1.0, phase_mode: int32 = _PHASE_MODE_DEFAULT,
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ref_time_mu: int64 = int64(-1), profile: int32 = DEFAULT_PROFILE,
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ram_destination: int32 = -1) -> float:
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"""Set DDS data in SI units.
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.. seealso:: :meth:`set_mu`
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@ -867,8 +865,8 @@ class AD9910:
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profile, ram_destination))
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@kernel
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def get(self, profile: TInt32 = DEFAULT_PROFILE
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) -> TTuple([TFloat, TFloat, TFloat]):
|
||||
def get(self, profile: int32 = DEFAULT_PROFILE
|
||||
) -> tuple[float, float, float]:
|
||||
"""Get the frequency, phase, and amplitude.
|
||||
|
||||
.. seealso:: :meth:`get_mu`
|
||||
|
|
@ -884,7 +882,7 @@ class AD9910:
|
|||
self.asf_to_amplitude(asf))
|
||||
|
||||
@kernel
|
||||
def set_att_mu(self, att: TInt32):
|
||||
def set_att_mu(self, att: int32):
|
||||
"""Set digital step attenuator in machine units.
|
||||
|
||||
This method will write the attenuator settings of all four channels.
|
||||
|
|
@ -896,7 +894,7 @@ class AD9910:
|
|||
self.cpld.set_att_mu(self.chip_select - 4, att)
|
||||
|
||||
@kernel
|
||||
def set_att(self, att: TFloat):
|
||||
def set_att(self, att: float):
|
||||
"""Set digital step attenuator in SI units.
|
||||
|
||||
This method will write the attenuator settings of all four channels.
|
||||
|
|
@ -908,7 +906,7 @@ class AD9910:
|
|||
self.cpld.set_att(self.chip_select - 4, att)
|
||||
|
||||
@kernel
|
||||
def get_att_mu(self) -> TInt32:
|
||||
def get_att_mu(self) -> int32:
|
||||
"""Get digital step attenuator value in machine units.
|
||||
|
||||
.. seealso:: :meth:`artiq.coredevice.urukul.CPLD.get_channel_att_mu`
|
||||
|
|
@ -918,7 +916,7 @@ class AD9910:
|
|||
return self.cpld.get_channel_att_mu(self.chip_select - 4)
|
||||
|
||||
@kernel
|
||||
def get_att(self) -> TFloat:
|
||||
def get_att(self) -> float:
|
||||
"""Get digital step attenuator value in SI units.
|
||||
|
||||
.. seealso:: :meth:`artiq.coredevice.urukul.CPLD.get_channel_att`
|
||||
|
|
@ -928,7 +926,7 @@ class AD9910:
|
|||
return self.cpld.get_channel_att(self.chip_select - 4)
|
||||
|
||||
@kernel
|
||||
def cfg_sw(self, state: TBool):
|
||||
def cfg_sw(self, state: bool):
|
||||
"""Set CPLD CFG RF switch state. The RF switch is controlled by the
|
||||
logical or of the CPLD configuration shift register
|
||||
RF switch bit and the SW TTL line (if used).
|
||||
|
|
@ -939,9 +937,9 @@ class AD9910:
|
|||
|
||||
@kernel
|
||||
def set_sync(self,
|
||||
in_delay: TInt32,
|
||||
window: TInt32,
|
||||
en_sync_gen: TInt32 = 0):
|
||||
in_delay: int32,
|
||||
window: int32,
|
||||
en_sync_gen: int32 = 0):
|
||||
"""Set the relevant parameters in the multi device synchronization
|
||||
register. See the AD9910 datasheet for details. The SYNC clock
|
||||
generator preset value is set to zero, and the SYNC_OUT generator is
|
||||
|
|
@ -981,7 +979,7 @@ class AD9910:
|
|||
|
||||
@kernel
|
||||
def tune_sync_delay(self,
|
||||
search_seed: TInt32 = 15) -> TTuple([TInt32, TInt32]):
|
||||
search_seed: int32 = 15) -> tuple[int32, int32]:
|
||||
"""Find a stable SYNC_IN delay.
|
||||
|
||||
This method first locates a valid SYNC_IN delay at zero validation
|
||||
|
|
@ -1037,8 +1035,8 @@ class AD9910:
|
|||
raise ValueError("no valid window/delay")
|
||||
|
||||
@kernel
|
||||
def measure_io_update_alignment(self, delay_start: TInt64,
|
||||
delay_stop: TInt64) -> TInt32:
|
||||
def measure_io_update_alignment(self, delay_start: int64,
|
||||
delay_stop: int64) -> int32:
|
||||
"""Use the digital ramp generator to locate the alignment between
|
||||
IO_UPDATE and SYNC_CLK.
|
||||
|
||||
|
|
@ -1080,7 +1078,7 @@ class AD9910:
|
|||
return ftw & 1
|
||||
|
||||
@kernel
|
||||
def tune_io_update_delay(self) -> TInt32:
|
||||
def tune_io_update_delay(self) -> int32:
|
||||
"""Find a stable IO_UPDATE delay alignment.
|
||||
|
||||
Scan through increasing IO_UPDATE delays until a delay is found that
|
||||
|
|
|
|||
Loading…
Reference in New Issue