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serwb/test: replace valid/ready with stb/ack

This commit is contained in:
Florent Kermarrec 2018-04-07 15:55:57 +02:00
parent 73dbc0b6b6
commit 6aa8e2c433
1 changed files with 5 additions and 5 deletions
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10
artiq/gateware/test/serwb/test_serwb_core.py
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@ -63,7 +63,7 @@ class DUTCore(Module):
phy_master.serdes.rx_ce.eq(phy_slave.serdes.tx_ce), phy_master.serdes.rx_ce.eq(phy_slave.serdes.tx_ce),
phy_master.serdes.rx_k.eq(phy_slave.serdes.tx_k), phy_master.serdes.rx_k.eq(phy_slave.serdes.tx_k),
phy_master.serdes.rx_d.eq(phy_slave.serdes.tx_d), phy_master.serdes.rx_d.eq(phy_slave.serdes.tx_d),
phy_slave.serdes.rx_ce.eq(phy_master.serdes.tx_ce), phy_slave.serdes.rx_ce.eq(phy_master.serdes.tx_ce),
phy_slave.serdes.rx_k.eq(phy_master.serdes.tx_k), phy_slave.serdes.rx_k.eq(phy_master.serdes.tx_k),
phy_slave.serdes.rx_d.eq(phy_master.serdes.tx_d) phy_slave.serdes.rx_d.eq(phy_master.serdes.tx_d)
@ -87,14 +87,14 @@ class TestSERWBCore(unittest.TestCase):
# test loop # test loop
while i != 256: while i != 256:
# stim # stim
yield dut.scrambler.sink.valid.eq(1) yield dut.scrambler.sink.stb.eq(1)
if (yield dut.scrambler.sink.valid) & (yield dut.scrambler.sink.ready): if (yield dut.scrambler.sink.stb) & (yield dut.scrambler.sink.ack):
i += 1 i += 1
yield dut.scrambler.sink.data.eq(i) yield dut.scrambler.sink.data.eq(i)
# check # check
yield dut.descrambler.source.ready.eq(prng.randrange(2)) yield dut.descrambler.source.ack.eq(prng.randrange(2))
if (yield dut.descrambler.source.valid) & (yield dut.descrambler.source.ready): if (yield dut.descrambler.source.stb) & (yield dut.descrambler.source.ack):
current_data = (yield dut.descrambler.source.data) current_data = (yield dut.descrambler.source.data)
if (current_data != (last_data + 1)): if (current_data != (last_data + 1)):
dut.errors += 1 dut.errors += 1