forked from M-Labs/artiq
Remove last vestiges of nist_qc1.
This commit is contained in:
whitequark
parent
5e8888d5f3
commit
6aa5d9f6c6
@ -24,13 +24,6 @@ class AD9xxx(Module):
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Design:
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All IO pads are registered.
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With QC1 adapter:
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LVDS driver/receiver propagation delays are 3.6+4.5 ns max
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LVDS state transition delays are 20, 15 ns max
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Schmitt trigger delays are 6.4ns max
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Round-trip addr A setup (> RX, RD, D to Z), RD prop, D valid (< D
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valid), D prop is ~15 + 10 + 20 + 10 = 55ns
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"""
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def __init__(self, pads,
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read_wait_cycles=10, hiz_wait_cycles=3,
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@ -1,54 +0,0 @@
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from migen.build.generic_platform import *
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papilio_adapter_io = [
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("ext_led", 0, Pins("B:7"), IOStandard("LVTTL")),
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# to feed the 125 MHz clock (preferrably from DDS SYNC_CLK)
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# to the FPGA, use the xtrig pair.
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#
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# on papiliopro-adapter, xtrig (C:12) is connected to a GCLK
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#
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# on pipistrello, C:15 is the only GCLK in proximity, used as a button
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# input, BTN2/PMT2 in papiliopro-adapter
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# either improve the DDS box to feed 125MHz into the PMT2 pair, or:
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#
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# * disconnect C:15 from its periphery on the adapter board
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# * bridge C:15 to the xtrig output of the transciever
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# * optionally, disconnect C:12 from its periphery
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("xtrig", 0, Pins("C:12"), IOStandard("LVTTL")),
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("pmt", 0, Pins("C:13"), IOStandard("LVTTL")),
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("pmt", 1, Pins("C:14"), IOStandard("LVTTL")),
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("pmt", 2, Pins("C:15"), IOStandard("LVTTL")), # rarely equipped
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("ttl", 0, Pins("C:11"), IOStandard("LVTTL")),
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("ttl", 1, Pins("C:10"), IOStandard("LVTTL")),
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("ttl", 2, Pins("C:9"), IOStandard("LVTTL")),
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("ttl", 3, Pins("C:8"), IOStandard("LVTTL")),
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("ttl", 4, Pins("C:7"), IOStandard("LVTTL")),
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("ttl", 5, Pins("C:6"), IOStandard("LVTTL")),
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("ttl", 6, Pins("C:5"), IOStandard("LVTTL")),
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("ttl", 7, Pins("C:4"), IOStandard("LVTTL")),
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("ttl_l_tx_en", 0, Pins("A:9"), IOStandard("LVTTL")),
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("ttl", 8, Pins("C:3"), IOStandard("LVTTL")),
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("ttl", 9, Pins("C:2"), IOStandard("LVTTL")),
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("ttl", 10, Pins("C:1"), IOStandard("LVTTL")),
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("ttl", 11, Pins("C:0"), IOStandard("LVTTL")),
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("ttl", 12, Pins("B:4"), IOStandard("LVTTL")),
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("ttl", 13, Pins("A:11"), IOStandard("LVTTL")),
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("ttl", 14, Pins("B:5"), IOStandard("LVTTL")),
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("ttl", 15, Pins("A:10"), IOStandard("LVTTL")),
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("ttl_h_tx_en", 0, Pins("B:6"), IOStandard("LVTTL")),
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("dds", 0,
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Subsignal("a", Pins("A:5 B:10 A:6 B:9 A:7 B:8")),
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Subsignal("d", Pins("A:12 B:3 A:13 B:2 A:14 B:1 A:15 B:0")),
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Subsignal("sel", Pins("A:2 B:14 A:1 B:15 A:0")),
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Subsignal("p", Pins("A:8 B:12")),
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Subsignal("fud_n", Pins("B:11")),
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Subsignal("wr_n", Pins("A:4")),
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Subsignal("rd_n", Pins("B:13")),
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Subsignal("rst_n", Pins("A:3")),
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IOStandard("LVTTL")),
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]
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@ -18,7 +18,7 @@ from misoc.targets.pipistrello import (BaseSoC, soc_pipistrello_args,
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from misoc.integration.builder import builder_args, builder_argdict
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from artiq.gateware.soc import AMPSoC, build_artiq_soc
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from artiq.gateware import rtio, nist_qc1
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_spartan6, dds, spi
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from artiq import __version__ as artiq_version
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@ -61,14 +61,14 @@ class _RTIOCRG(Module, AutoCSR):
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f = Fraction(rtio_f, clk_freq)
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rtio_internal_clk = Signal()
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rtio_external_clk = Signal()
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pmt2 = platform.request("pmt", 2)
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ext_clk = platform.request("ext_clk")
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dcm_locked = Signal()
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rtio_clk = Signal()
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pll_locked = Signal()
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pll = Signal(3)
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pll_fb = Signal()
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self.specials += [
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Instance("IBUFG", i_I=pmt2, o_O=rtio_external_clk),
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Instance("IBUFG", i_I=ext_clk, o_O=rtio_external_clk),
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Instance("DCM_CLKGEN", p_CLKFXDV_DIVIDE=2,
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p_CLKFX_DIVIDE=f.denominator, p_CLKFX_MD_MAX=float(f),
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p_CLKFX_MULTIPLY=f.numerator, p_CLKIN_PERIOD=1e9/clk_freq,
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@ -124,7 +124,30 @@ TIMESPEC "TSfix_ise4" = FROM "GRPsys_clk" TO "GRPrtio_clk" TIG;
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rtio_clk=self.cd_rtio.clk)
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class NIST_QC1(BaseSoC, AMPSoC):
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_ttl_io = [
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("ext_clk", 0, Pins("C:15"), IOStandard("LVTTL")),
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("ttl", 0, Pins("B:0"), IOStandard("LVTTL")),
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("ttl", 1, Pins("B:1"), IOStandard("LVTTL")),
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("ttl", 2, Pins("B:2"), IOStandard("LVTTL")),
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("ttl", 3, Pins("B:3"), IOStandard("LVTTL")),
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("ttl", 4, Pins("B:4"), IOStandard("LVTTL")),
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("ttl", 5, Pins("B:5"), IOStandard("LVTTL")),
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("ttl", 6, Pins("B:6"), IOStandard("LVTTL")),
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("ttl", 7, Pins("B:7"), IOStandard("LVTTL")),
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("ttl", 8, Pins("B:8"), IOStandard("LVTTL")),
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("ttl", 9, Pins("B:9"), IOStandard("LVTTL")),
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("ttl", 10, Pins("B:10"), IOStandard("LVTTL")),
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("ttl", 11, Pins("B:11"), IOStandard("LVTTL")),
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("ttl", 12, Pins("B:12"), IOStandard("LVTTL")),
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("ttl", 13, Pins("B:13"), IOStandard("LVTTL")),
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("ttl", 14, Pins("B:14"), IOStandard("LVTTL")),
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("ttl", 15, Pins("B:15"), IOStandard("LVTTL")),
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]
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class Demo(BaseSoC, AMPSoC):
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mem_map = {
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"timer_kernel": 0x10000000, # (shadow @0x90000000)
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"rtio": 0x20000000, # (shadow @0xa0000000)
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@ -148,29 +171,16 @@ class NIST_QC1(BaseSoC, AMPSoC):
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platform.toolchain.ise_commands += """
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trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd {build_name}.pcf
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"""
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platform.add_extension(nist_qc1.papilio_adapter_io)
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platform.add_extension(_ttl_io)
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platform.add_extension(_pmod_spi)
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self.submodules.leds = gpio.GPIOOut(platform.request("user_led", 4))
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self.comb += [
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platform.request("ttl_l_tx_en").eq(1),
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platform.request("ttl_h_tx_en").eq(1)
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]
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self.submodules.rtio_crg = _RTIOCRG(platform, self.clk_freq)
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self.csr_devices.append("rtio_crg")
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# RTIO channels
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rtio_channels = []
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# pmt1 can run on a 8x serdes if pmt0 is not used
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for i in range(2):
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phy = ttl_serdes_spartan6.Inout_4X(platform.request("pmt", i),
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self.rtio_crg.rtiox4_stb)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128,
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ofifo_depth=4))
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# the last TTL is used for ClockGen
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for i in range(15):
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if i in (0, 1):
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@ -185,10 +195,6 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=128))
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phy = ttl_simple.Output(platform.request("ext_led", 0))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4))
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for led_number in range(4):
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phy = ttl_simple.Output(platform.request("user_led", led_number))
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self.submodules += phy
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@ -212,7 +218,6 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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# RTIO logic
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self.submodules.rtio = rtio.RTIO(rtio_channels)
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self.register_kernel_cpu_csrdevice("rtio")
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self.config["DDS_RTIO_CLK_RATIO"] = 8 >> self.rtio.fine_ts_width
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.rtio_analyzer = rtio.Analyzer(
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@ -222,13 +227,12 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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def main():
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parser = argparse.ArgumentParser(
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description="ARTIQ core device builder / Pipistrello "
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"+ NIST Ions QC1 hardware adapter")
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description="ARTIQ core device builder / Pipistrello demo")
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builder_args(parser)
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soc_pipistrello_args(parser)
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args = parser.parse_args()
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soc = NIST_QC1(**soc_pipistrello_argdict(args))
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soc = Demo(**soc_pipistrello_argdict(args))
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build_artiq_soc(soc, builder_argdict(args))
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@ -3,12 +3,12 @@
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BUILD_SETTINGS_FILE=$HOME/.m-labs/build_settings.sh
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[ -f $BUILD_SETTINGS_FILE ] && . $BUILD_SETTINGS_FILE
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SOC_PREFIX=$PREFIX/lib/python3.5/site-packages/artiq/binaries/pipistrello-nist_qc1
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SOC_PREFIX=$PREFIX/lib/python3.5/site-packages/artiq/binaries/pipistrello-demo
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mkdir -p $SOC_PREFIX
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$PYTHON -m artiq.gateware.targets.pipistrello $MISOC_EXTRA_ISE_CMDLINE
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cp misoc_nist_qc1_pipistrello/gateware/top.bit $SOC_PREFIX
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cp misoc_nist_qc1_pipistrello/software/bios/bios.bin $SOC_PREFIX
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cp misoc_nist_qc1_pipistrello/software/runtime/runtime.fbi $SOC_PREFIX
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cp misoc_demo_pipistrello/gateware/top.bit $SOC_PREFIX
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cp misoc_demo_pipistrello/software/bios/bios.bin $SOC_PREFIX
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cp misoc_demo_pipistrello/software/runtime/runtime.fbi $SOC_PREFIX
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wget -P $SOC_PREFIX https://raw.githubusercontent.com/jordens/bscan_spi_bitstreams/master/bscan_spi_xc6slx45.bit
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@ -1,5 +1,5 @@
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package:
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name: artiq-pipistrello-nist_qc1
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name: artiq-pipistrello-demo
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version: {{ environ.get("GIT_DESCRIBE_TAG", "") }}
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source:
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@ -24,4 +24,4 @@ requirements:
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about:
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home: http://m-labs.hk/artiq
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license: GPL
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summary: 'Bitstream, BIOS and runtime for NIST_QC1 on the Pipistrello board'
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summary: 'Bitstream, BIOS and runtime for the Pipistrello board'
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@ -141,33 +141,25 @@ The low-cost Pipistrello FPGA board can be used as a lower-cost but slower alter
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.. warning:: The Pipistrello draws a high current over USB, and that current increases when the FPGA design is active. If you experience problems such as intermittent board freezes or USB errors, try connecting it to a self-powered USB hub.
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When plugged to an adapter, the NIST QC1 hardware can be used. The TTL lines are mapped to RTIO channels as follows:
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The TTL lines are mapped to RTIO channels as follows:
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+--------------+------------+--------------+
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| RTIO channel | TTL line | Capability |
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+==============+============+==============+
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| 0 | PMT0 | Input |
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| 0-14 | B0-14 | Output |
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+--------------+------------+--------------+
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| 1 | PMT1 | Input |
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| 15 | USER_LED_1 | Output |
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+--------------+------------+--------------+
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| 2-16 | TTL0-14 | Output |
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| 16 | USER_LED_2 | Output |
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+--------------+------------+--------------+
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| 17 | EXT_LED | Output |
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| 17 | USER_LED_3 | Output |
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+--------------+------------+--------------+
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| 18 | USER_LED_1 | Output |
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| 18 | USER_LED_4 | Output |
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+--------------+------------+--------------+
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| 19 | USER_LED_2 | Output |
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+--------------+------------+--------------+
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| 20 | USER_LED_3 | Output |
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+--------------+------------+--------------+
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| 21 | USER_LED_4 | Output |
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+--------------+------------+--------------+
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| 22 | TTL15 | Clock |
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| 19 | B15 | Clock |
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+--------------+------------+--------------+
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The input only limitation on channels 0 and 1 comes from the QC-DAQ adapter. When the adapter is not used (and physically unplugged from the Pipistrello board), the corresponding pins on the Pipistrello can be used as outputs. Do not configure these channels as outputs when the adapter is plugged, as this would cause electrical contention.
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The board can accept an external RTIO clock connected to PMT2. If the DDS box does not drive the PMT2 pair, use XTRIG and patch the XTRIG transceiver output on the adapter board onto C:15 disconnecting PMT2.
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The board can accept an external RTIO clock connected to C15.
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The board has one RTIO SPI bus on the PMOD connector, compliant to PMOD
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Interface Type 2 (SPI) and 2A (expanded SPI):
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@ -175,5 +167,5 @@ Interface Type 2 (SPI) and 2A (expanded SPI):
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+--------------+--------+--------+--------+--------+
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| RTIO channel | CS_N | MOSI | MISO | CLK |
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+==============+========+========+========+========+
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| 23 | PMOD_0 | PMOD_1 | PMOD_2 | PMOD_3 |
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| 16 | PMOD_0 | PMOD_1 | PMOD_2 | PMOD_3 |
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+--------------+--------+--------+--------+--------+
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@ -43,13 +43,13 @@ Then prepare to create a new conda environment with the ARTIQ package and the ma
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choose a suitable name for the environment, for example ``artiq-main`` if you intend to track the main label or ``artiq-2016-04-01`` if you consider the environment a snapshot of ARTIQ on 2016-04-01.
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Choose the package containing the binaries for your hardware:
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* ``artiq-pipistrello-nist_qc1`` for the `Pipistrello <http://pipistrello.saanlima.com/>`_ board with the NIST adapter to SCSI cables; AD9858 DDS chips are not supported anymore.
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* ``artiq-pipistrello-demo`` for the `Pipistrello <http://pipistrello.saanlima.com/>`_ board.
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* ``artiq-kc705-nist_clock`` for the KC705 board with the NIST "clock" FMC backplane and AD9914 DDS chips.
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* ``artiq-kc705-nist_qc2`` for the KC705 board with the NIST QC2 FMC backplane and AD9914 DDS chips.
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Conda will create the environment, automatically resolve, download, and install the necessary dependencies and install the packages you select::
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$ conda create -n artiq-main artiq-pipistrello-nist_qc1
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$ conda create -n artiq-main artiq-pipistrello-demo
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After the installation, activate the newly created environment by name.
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On Unix::
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@ -79,7 +79,7 @@ When upgrading ARTIQ or when testing different versions it is recommended that n
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Keep previous environments around until you are certain that they are not needed anymore and a new environment is known to work correctly.
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You can create a new conda environment specifically to test a certain version of ARTIQ::
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$ conda create -n artiq-test-1.0rc2 artiq-pipistrello-nist_qc1=1.0rc2
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$ conda create -n artiq-test-1.0rc2 artiq-pipistrello-demo=1.0rc2
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Switching between conda environments using ``$ source deactivate artiq-1.0rc2`` and ``$ source activate artiq-1.0rc1`` is the recommended way to roll back to previous versions of ARTIQ.
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You can list the environments you have created using::
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@ -131,7 +131,7 @@ Then, you can flash the board:
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* For the Pipistrello board::
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$ artiq_flash -t pipistrello -m nist_qc1
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$ artiq_flash -t pipistrello -m demo
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* For the KC705 board (selecting the appropriate hardware peripheral)::
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Block a user