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Commit missing parts of 7f914a0.

This commit is contained in:
whitequark 2016-01-10 20:25:58 +00:00
parent 225f7d7302
commit 63f7899f93
1 changed files with 2 additions and 1 deletions
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3
artiq/compiler/transforms/llvm_ir_generator.py
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@ -191,6 +191,7 @@ class LLVMIRGenerator:
and len(lltyp.elements) <= 2: and len(lltyp.elements) <= 2:
return not any([self.needs_sret(elt, may_be_large=False) for elt in lltyp.elements]) return not any([self.needs_sret(elt, may_be_large=False) for elt in lltyp.elements])
else: else:
assert isinstance(lltyp, ll.Type)
return True return True
def has_sret(self, functy): def has_sret(self, functy):
@ -1239,7 +1240,7 @@ class LLVMIRGenerator:
return self.llbuilder.ret_void() return self.llbuilder.ret_void()
else: else:
llvalue = self.map(insn.value()) llvalue = self.map(insn.value())
if self.needs_sret(llvalue): if self.needs_sret(llvalue.type):
self.llbuilder.store(llvalue, self.llfunction.args[0]) self.llbuilder.store(llvalue, self.llfunction.args[0])
return self.llbuilder.ret_void() return self.llbuilder.ret_void()
else: else: