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updated adoo10.py for RAM mode frequency control

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This commit is contained in:
Garrett 2019-11-05 14:54:20 -06:00 committed by Robert Jördens
parent fd7081830c
commit 61ca46ec3f
1 changed files with 6 additions and 2 deletions
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8
artiq/coredevice/ad9910.py
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@ -345,7 +345,8 @@ class AD9910:
@kernel
def set_cfr1(self, power_down=0b0000, phase_autoclear=0,
drg_load_lrr=0, drg_autoclear=0,
internal_profile=0, ram_destination=0, ram_enable=0):
internal_profile=0, ram_destination=0, ram_enable=0,
manual_osk_external=0, osk_enable=0, select_auto_osk=0):
"""Set CFR1. See the AD9910 datasheet for parameter meanings.
This method does not pulse IO_UPDATE.
@ -363,10 +364,13 @@ class AD9910:
self.write32(_AD9910_REG_CFR1,
(ram_enable << 31) |
(ram_destination << 29) |
(manual_osk_external << 23) |
(internal_profile << 17) |
(drg_load_lrr << 15) |
(drg_autoclear << 14) |
(phase_autoclear << 13) |
(osk_enable << 9) |
(select_auto_osk << 8) |
(power_down << 4) |
2) # SDIO input only, MSB first
@ -526,7 +530,7 @@ class AD9910:
@kernel
def set_asf(self, asf):
self.write32(_AD9910_REG_ASF, asf)
self.write32(_AD9910_REG_ASF, asf<<2)
@kernel
def set_pow(self, pow_):