occheung
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

rtio/dma: fix signal width

This commit is contained in:
Sebastien Bourdeauducq 2017-10-08 22:37:46 +08:00
parent 6c049ad40c
commit 5f083f21a4
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
artiq/gateware/rtio/dma.py
View File

@ -254,7 +254,7 @@ class CRIMaster(Module, AutoCSR):
# # # # # #
underflow_trigger = Signal(2) underflow_trigger = Signal()
self.sync += [ self.sync += [
If(underflow_trigger, If(underflow_trigger,
self.underflow.w.eq(1), self.underflow.w.eq(1),