forked from M-Labs/artiq
sayma_rtm: support setting RTIO frequency
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parent
da9237de53
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57a5bea43a
@ -73,7 +73,7 @@ class _SatelliteBase(BaseSoC):
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, rtio_clk_freq=150e6, **kwargs):
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def __init__(self, rtio_clk_freq, **kwargs):
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BaseSoC.__init__(self,
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cpu_type="or1k",
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**kwargs)
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@ -207,7 +207,7 @@ class Satellite(_SatelliteBase):
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self.config["CONVERTER_SPI_HMC830_CS"] = 0
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self.config["CONVERTER_SPI_HMC7043_CS"] = 1
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self.config["CONVERTER_SPI_FIRST_AD9154_CS"] = 2
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self.config["HMC830_REF"] = "150"
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self.config["HMC830_REF"] = str(int(self.rtio_clk_freq/1e6))
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# HMC workarounds
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self.comb += platform.request("hmc830_pwr_en").eq(1)
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@ -243,10 +243,13 @@ def main():
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description="Sayma RTM gateware and firmware builder")
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builder_args(parser)
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soc_sayma_rtm_args(parser)
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parser.add_argument("--rtio-clk-freq",
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default=150, type=int, help="RTIO clock frequency in MHz")
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parser.set_defaults(output_dir=os.path.join("artiq_sayma", "rtm"))
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args = parser.parse_args()
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soc = Satellite(**soc_sayma_rtm_argdict(args))
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soc = Satellite(rtio_clk_freq=1e6*args.rtio_clk_freq,
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**soc_sayma_rtm_argdict(args))
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builder = SatmanSoCBuilder(soc, **builder_argdict(args))
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try:
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builder.build()
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