forked from M-Labs/artiq
kasli: add tester target
This commit is contained in:
parent
2e6b81d59a
commit
4e5fe672e7
187
artiq/examples/kasli_basic/device_db_tester.py
Normal file
187
artiq/examples/kasli_basic/device_db_tester.py
Normal file
@ -0,0 +1,187 @@
|
||||
core_addr = "kasli-2.lab.m-labs.hk"
|
||||
|
||||
device_db = {
|
||||
"core": {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.core",
|
||||
"class": "Core",
|
||||
"arguments": {"host": core_addr, "ref_period": 1e-9}
|
||||
},
|
||||
"core_log": {
|
||||
"type": "controller",
|
||||
"host": "::1",
|
||||
"port": 1068,
|
||||
"command": "aqctl_corelog -p {port} --bind {bind} " + core_addr
|
||||
},
|
||||
"core_cache": {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.cache",
|
||||
"class": "CoreCache"
|
||||
},
|
||||
"core_dma": {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.dma",
|
||||
"class": "CoreDMA"
|
||||
},
|
||||
|
||||
"i2c_switch0": {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.i2c",
|
||||
"class": "PCA9548",
|
||||
"arguments": {"address": 0xe0}
|
||||
},
|
||||
"i2c_switch1": {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.i2c",
|
||||
"class": "PCA9548",
|
||||
"arguments": {"address": 0xe2}
|
||||
},
|
||||
}
|
||||
|
||||
|
||||
for i in range(8):
|
||||
device_db["ttl" + str(i)] = {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.ttl",
|
||||
"class": "TTLInOut" if i < 4 else "TTLOut",
|
||||
"arguments": {"channel": i},
|
||||
}
|
||||
|
||||
|
||||
device_db.update(
|
||||
spi_urukul0={
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.spi2",
|
||||
"class": "SPIMaster",
|
||||
"arguments": {"channel": 8}
|
||||
},
|
||||
ttl_urukul0_io_update={
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.ttl",
|
||||
"class": "TTLOut",
|
||||
"arguments": {"channel": 9}
|
||||
},
|
||||
ttl_urukul0_sw0={
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.ttl",
|
||||
"class": "TTLOut",
|
||||
"arguments": {"channel": 10}
|
||||
},
|
||||
ttl_urukul0_sw1={
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.ttl",
|
||||
"class": "TTLOut",
|
||||
"arguments": {"channel": 11}
|
||||
},
|
||||
ttl_urukul0_sw2={
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.ttl",
|
||||
"class": "TTLOut",
|
||||
"arguments": {"channel": 12}
|
||||
},
|
||||
ttl_urukul0_sw3={
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.ttl",
|
||||
"class": "TTLOut",
|
||||
"arguments": {"channel": 13}
|
||||
},
|
||||
urukul0_cpld={
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.urukul",
|
||||
"class": "CPLD",
|
||||
"arguments": {
|
||||
"spi_device": "spi_urukul0",
|
||||
"io_update_device": "ttl_urukul0_io_update",
|
||||
"refclk": 125e6,
|
||||
"clk_sel": 0
|
||||
}
|
||||
}
|
||||
)
|
||||
|
||||
for i in range(4):
|
||||
device_db["urukul0_ch" + str(i)] = {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.ad9910",
|
||||
"class": "AD9910",
|
||||
"arguments": {
|
||||
"pll_n": 32,
|
||||
"chip_select": 4 + i,
|
||||
"cpld_device": "urukul0_cpld",
|
||||
"sw_device": "ttl_urukul0_sw" + str(i)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
device_db["spi_sampler0_adc"] = {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.spi2",
|
||||
"class": "SPIMaster",
|
||||
"arguments": {"channel": 14}
|
||||
}
|
||||
device_db["spi_sampler0_pgia"] = {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.spi2",
|
||||
"class": "SPIMaster",
|
||||
"arguments": {"channel": 15}
|
||||
}
|
||||
device_db["spi_sampler0_cnv"] = {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.ttl",
|
||||
"class": "TTLOut",
|
||||
"arguments": {"channel": 16},
|
||||
}
|
||||
device_db["sampler0"] = {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.sampler",
|
||||
"class": "Sampler",
|
||||
"arguments": {
|
||||
"spi_adc_device": "spi_sampler0_adc",
|
||||
"spi_pgia_device": "spi_sampler0_pgia",
|
||||
"cnv_device": "spi_sampler0_cnv"
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
device_db["spi_zotino0"] = {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.spi2",
|
||||
"class": "SPIMaster",
|
||||
"arguments": {"channel": 17}
|
||||
}
|
||||
device_db["ttl_zotino0_ldac"] = {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.ttl",
|
||||
"class": "TTLOut",
|
||||
"arguments": {"channel": 18}
|
||||
}
|
||||
device_db["ttl_zotino0_clr"] = {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.ttl",
|
||||
"class": "TTLOut",
|
||||
"arguments": {"channel": 19}
|
||||
}
|
||||
device_db["zotino0"] = {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.zotino",
|
||||
"class": "Zotino",
|
||||
"arguments": {
|
||||
"spi_device": "spi_zotino0",
|
||||
"ldac_device": "ttl_zotino0_ldac",
|
||||
"clr_device": "ttl_zotino0_clr"
|
||||
}
|
||||
}
|
||||
|
||||
device_db.update(
|
||||
led0={
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.ttl",
|
||||
"class": "TTLOut",
|
||||
"arguments": {"channel": 20}
|
||||
},
|
||||
led1={
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.ttl",
|
||||
"class": "TTLOut",
|
||||
"arguments": {"channel": 21}
|
||||
},
|
||||
)
|
||||
@ -269,7 +269,7 @@ def main():
|
||||
"kasli": {
|
||||
"programmer": partial(ProgrammerXC7, board="kasli", proxy="bscan_spi_xc7a100t.bit"),
|
||||
"variants": ["opticlock", "suservo", "sysu", "mitll", "ustc",
|
||||
"master", "satellite"],
|
||||
"tester", "master", "satellite"],
|
||||
"gateware": ("spi0", 0x000000),
|
||||
"bootloader": ("spi0", 0x400000),
|
||||
"storage": ("spi0", 0x440000),
|
||||
|
||||
@ -787,6 +787,101 @@ class USTC(_StandaloneBase):
|
||||
self.add_rtio(rtio_channels)
|
||||
|
||||
|
||||
class Tester(_StandaloneBase):
|
||||
"""
|
||||
Configuration for CI tests. Contains the maximum number of different EEMs.
|
||||
"""
|
||||
def __init__(self, hw_rev=None, **kwargs):
|
||||
if hw_rev is None:
|
||||
hw_rev = "v1.1"
|
||||
_StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
|
||||
|
||||
self.config["SI5324_AS_SYNTHESIZER"] = None
|
||||
# self.config["SI5324_EXT_REF"] = None
|
||||
self.config["RTIO_FREQUENCY"] = "125.0"
|
||||
|
||||
platform = self.platform
|
||||
platform.add_extension(_urukul("eem1", "eem0"))
|
||||
platform.add_extension(_sampler("eem3", "eem2"))
|
||||
platform.add_extension(_zotino("eem4"))
|
||||
platform.add_extension(_dio("eem5"))
|
||||
|
||||
try:
|
||||
# EEM clock fan-out from Si5324, not MMCX, only Kasli/v1.0
|
||||
self.comb += platform.request("clk_sel").eq(1)
|
||||
except ConstraintError:
|
||||
pass
|
||||
|
||||
# EEM5: TTL
|
||||
rtio_channels = []
|
||||
for i in range(8):
|
||||
pads = platform.request("eem5", i)
|
||||
if i < 4:
|
||||
cls = ttl_serdes_7series.InOut_8X
|
||||
else:
|
||||
cls = ttl_serdes_7series.Output_8X
|
||||
phy = cls(pads.p, pads.n)
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel.from_phy(phy))
|
||||
|
||||
# EEM0, EEM1: Urukul
|
||||
phy = spi2.SPIMaster(self.platform.request("eem1_spi_p"),
|
||||
self.platform.request("eem1_spi_n"))
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
|
||||
|
||||
pads = platform.request("eem1_dds_reset")
|
||||
self.specials += DifferentialOutput(0, pads.p, pads.n)
|
||||
|
||||
for signal in "io_update sw0 sw1 sw2 sw3".split():
|
||||
pads = platform.request("eem1_{}".format(signal))
|
||||
phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel.from_phy(phy))
|
||||
|
||||
# EEM2, EEM3: Sampler
|
||||
phy = spi2.SPIMaster(self.platform.request("eem3_adc_spi_p"),
|
||||
self.platform.request("eem3_adc_spi_n"))
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
|
||||
phy = spi2.SPIMaster(self.platform.request("eem3_pgia_spi_p"),
|
||||
self.platform.request("eem3_pgia_spi_n"))
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
|
||||
pads = platform.request("eem3_cnv")
|
||||
phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel.from_phy(phy))
|
||||
sdr = platform.request("eem3_sdr")
|
||||
self.specials += DifferentialOutput(1, sdr.p, sdr.n)
|
||||
|
||||
# EEM4: Zotino
|
||||
phy = spi2.SPIMaster(self.platform.request("eem4_spi_p"),
|
||||
self.platform.request("eem4_spi_n"))
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
|
||||
|
||||
for signal in "ldac_n clr_n".split():
|
||||
pads = platform.request("eem4_{}".format(signal))
|
||||
phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel.from_phy(phy))
|
||||
|
||||
for i in (1, 2):
|
||||
sfp_ctl = platform.request("sfp_ctl", i)
|
||||
phy = ttl_simple.Output(sfp_ctl.led)
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel.from_phy(phy))
|
||||
|
||||
print(len(rtio_channels))
|
||||
|
||||
self.config["HAS_RTIO_LOG"] = None
|
||||
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
|
||||
rtio_channels.append(rtio.LogChannel())
|
||||
|
||||
self.add_rtio(rtio_channels)
|
||||
|
||||
|
||||
class _RTIOClockMultiplier(Module):
|
||||
def __init__(self, rtio_clk_freq):
|
||||
self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
|
||||
@ -1098,7 +1193,7 @@ def main():
|
||||
parser.set_defaults(output_dir="artiq_kasli")
|
||||
parser.add_argument("-V", "--variant", default="opticlock",
|
||||
help="variant: opticlock/suservo/sysu/mitll/ustc/"
|
||||
"master/satellite "
|
||||
"tester/master/satellite "
|
||||
"(default: %(default)s)")
|
||||
args = parser.parse_args()
|
||||
|
||||
@ -1113,6 +1208,8 @@ def main():
|
||||
cls = MITLL
|
||||
elif variant == "ustc":
|
||||
cls = USTC
|
||||
elif variant == "tester":
|
||||
cls = Tester
|
||||
elif variant == "master":
|
||||
cls = Master
|
||||
elif variant == "satellite":
|
||||
|
||||
Loading…
Reference in New Issue
Block a user