forked from M-Labs/artiq
sawg: fix limit regs
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708c25b83a
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4c27029be0
@ -108,7 +108,7 @@ class Config(Module):
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Signal((width, True), reset=(1 << width - 1) - 1)]
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for i in range(3)]
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self.clipped = [Signal(2) for i in range(3)] # TODO
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self.i = Endpoint([("addr", bits_for(4 + len(self.limits))),
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self.i = Endpoint([("addr", bits_for(1 + 4 + len(self.limits))),
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("data", 16)])
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self.ce = Signal()
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@ -119,7 +119,7 @@ class Config(Module):
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pad = Signal()
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reg = Array([Cat(div, n), self.clr, self.iq_en, pad] +
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[Cat(*l) for l in self.limits])
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sum(self.limits, []))
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self.comb += [
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self.i.ack.eq(1),
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