ad9858: make wb data 8 bit wide

matches actual dds bus data width and saves bram
2015-06-20 23:33:55 -06:00 · 2015-06-20 23:33:55 -06:00 · 45ec5dbe84
commit 45ec5dbe84
parent c8fba45db5
1 changed files with 1 additions and 1 deletions
--- a/artiq/gateware/ad9858.py
+++ b/artiq/gateware/ad9858.py
@ -38,7 +38,7 @@ class AD9858(Module):
                 read_wait_cycles=10, hiz_wait_cycles=3,
                 bus=None):
        if bus is None:
-            bus = wishbone.Interface()
+            bus = wishbone.Interface(data_width=8)
        self.bus = bus

        # # #