forked from M-Labs/artiq
1
0
Fork 0

compiler: switch to upstream llvmlite and RISC-V target

This commit is contained in:
Sebastien Bourdeauducq 2021-08-12 11:54:36 +08:00 committed by occheung
parent 5656e52581
commit 43d120359d
12 changed files with 27 additions and 28 deletions

View File

@ -1,6 +1,6 @@
import os, sys, tempfile, subprocess, io import os, sys, tempfile, subprocess, io
from artiq.compiler import types, ir from artiq.compiler import types, ir
from llvmlite_artiq import ir as ll, binding as llvm from llvmlite import ir as ll, binding as llvm
llvm.initialize() llvm.initialize()
llvm.initialize_all_targets() llvm.initialize_all_targets()
@ -67,7 +67,7 @@ class Target:
generated by the ARTIQ compiler will be deployed. generated by the ARTIQ compiler will be deployed.
:var triple: (string) :var triple: (string)
LLVM target triple, e.g. ``"or1k"`` LLVM target triple, e.g. ``"riscv32"``
:var data_layout: (string) :var data_layout: (string)
LLVM target data layout, e.g. ``"E-m:e-p:32:32-i64:32-f64:32-v64:32-v128:32-a:0:32-n32"`` LLVM target data layout, e.g. ``"E-m:e-p:32:32-i64:32-f64:32-v64:32-v128:32-a:0:32-n32"``
:var features: (list of string) :var features: (list of string)
@ -255,19 +255,18 @@ class NativeTarget(Target):
assert host_data_layout[0] in "eE" assert host_data_layout[0] in "eE"
self.little_endian = host_data_layout[0] == "e" self.little_endian = host_data_layout[0] == "e"
class OR1KTarget(Target): class RISCVTarget(Target):
triple = "or1k-linux" triple = "riscv32-unknown-linux"
data_layout = "E-m:e-p:32:32-i8:8:8-i16:16:16-i64:32:32-" \ data_layout = "e-m:e-p:32:32-i64:64-n32-S128"
"f64:32:32-v64:32:32-v128:32:32-a0:0:32-n32" features = []
features = ["mul", "div", "ffl1", "cmov", "addc"]
print_function = "core_log" print_function = "core_log"
little_endian = False little_endian = False
now_pinning = True now_pinning = True
tool_ld = "or1k-linux-ld" tool_ld = "ld.lld"
tool_strip = "or1k-linux-strip" tool_strip = "llvm-strip"
tool_addr2line = "or1k-linux-addr2line" tool_addr2line = "llvm-addr2line"
tool_cxxfilt = "or1k-linux-c++filt" tool_cxxfilt = "llvm-cxxfilt"
class CortexA9Target(Target): class CortexA9Target(Target):
triple = "armv7-unknown-linux-gnueabihf" triple = "armv7-unknown-linux-gnueabihf"

View File

@ -1,6 +1,6 @@
import os, sys, fileinput, ctypes import os, sys, fileinput, ctypes
from pythonparser import diagnostic from pythonparser import diagnostic
from llvmlite_artiq import binding as llvm from llvmlite import binding as llvm
from ..module import Module, Source from ..module import Module, Source
from ..targets import NativeTarget from ..targets import NativeTarget

View File

@ -1,6 +1,6 @@
import sys, fileinput import sys, fileinput
from pythonparser import diagnostic from pythonparser import diagnostic
from llvmlite_artiq import ir as ll from llvmlite import ir as ll
from ..module import Module, Source from ..module import Module, Source
from ..targets import NativeTarget from ..targets import NativeTarget

View File

@ -1,7 +1,7 @@
import sys, os import sys, os
from pythonparser import diagnostic from pythonparser import diagnostic
from ..module import Module, Source from ..module import Module, Source
from ..targets import OR1KTarget from ..targets import RISCVTarget
from . import benchmark from . import benchmark
def main(): def main():
@ -30,7 +30,7 @@ def main():
benchmark(lambda: Module(source), benchmark(lambda: Module(source),
"ARTIQ transforms and validators") "ARTIQ transforms and validators")
benchmark(lambda: OR1KTarget().compile_and_link([module]), benchmark(lambda: RISCVTarget().compile_and_link([module]),
"LLVM optimization and linking") "LLVM optimization and linking")
if __name__ == "__main__": if __name__ == "__main__":

View File

@ -5,7 +5,7 @@ from ...master.databases import DeviceDB, DatasetDB
from ...master.worker_db import DeviceManager, DatasetManager from ...master.worker_db import DeviceManager, DatasetManager
from ..module import Module from ..module import Module
from ..embedding import Stitcher from ..embedding import Stitcher
from ..targets import OR1KTarget from ..targets import RISCVTarget
from . import benchmark from . import benchmark
@ -45,7 +45,7 @@ def main():
stitcher = embed() stitcher = embed()
module = Module(stitcher) module = Module(stitcher)
target = OR1KTarget() target = RISCVTarget()
llvm_ir = target.compile(module) llvm_ir = target.compile(module)
elf_obj = target.assemble(llvm_ir) elf_obj = target.assemble(llvm_ir)
elf_shlib = target.link([elf_obj]) elf_shlib = target.link([elf_obj])

View File

@ -1,7 +1,7 @@
import sys, os import sys, os
from pythonparser import diagnostic from pythonparser import diagnostic
from ..module import Module, Source from ..module import Module, Source
from ..targets import OR1KTarget from ..targets import RISCVTarget
def main(): def main():
if not len(sys.argv) > 1: if not len(sys.argv) > 1:
@ -20,7 +20,7 @@ def main():
for filename in sys.argv[1:]: for filename in sys.argv[1:]:
modules.append(Module(Source.from_filename(filename, engine=engine))) modules.append(Module(Source.from_filename(filename, engine=engine)))
llobj = OR1KTarget().compile_and_link(modules) llobj = RISCVTarget().compile_and_link(modules)
basename, ext = os.path.splitext(sys.argv[-1]) basename, ext = os.path.splitext(sys.argv[-1])
with open(basename + ".so", "wb") as f: with open(basename + ".so", "wb") as f:

View File

@ -6,7 +6,7 @@ into LLVM intermediate representation.
import os, re, types as pytypes, numpy import os, re, types as pytypes, numpy
from collections import defaultdict from collections import defaultdict
from pythonparser import ast, diagnostic from pythonparser import ast, diagnostic
from llvmlite_artiq import ir as ll, binding as llvm from llvmlite import ir as ll, binding as llvm
from ...language import core as language_core from ...language import core as language_core
from .. import types, builtins, ir from .. import types, builtins, ir
from ..embedding import SpecializedFunction from ..embedding import SpecializedFunction

View File

@ -11,7 +11,7 @@ from artiq.language.units import *
from artiq.compiler.module import Module from artiq.compiler.module import Module
from artiq.compiler.embedding import Stitcher from artiq.compiler.embedding import Stitcher
from artiq.compiler.targets import OR1KTarget, CortexA9Target from artiq.compiler.targets import RISCVTarget, CortexA9Target
from artiq.coredevice.comm_kernel import CommKernel, CommKernelDummy from artiq.coredevice.comm_kernel import CommKernel, CommKernelDummy
# Import for side effects (creating the exception classes). # Import for side effects (creating the exception classes).
@ -71,11 +71,11 @@ class Core:
"core", "ref_period", "coarse_ref_period", "ref_multiplier", "core", "ref_period", "coarse_ref_period", "ref_multiplier",
} }
def __init__(self, dmgr, host, ref_period, ref_multiplier=8, target="or1k"): def __init__(self, dmgr, host, ref_period, ref_multiplier=8, target="riscv"):
self.ref_period = ref_period self.ref_period = ref_period
self.ref_multiplier = ref_multiplier self.ref_multiplier = ref_multiplier
if target == "or1k": if target == "riscv":
self.target_cls = OR1KTarget self.target_cls = RISCVTarget
elif target == "cortexa9": elif target == "cortexa9":
self.target_cls = CortexA9Target self.target_cls = CortexA9Target
else: else:

View File

@ -15,7 +15,7 @@ def process_header(output, description):
raise NotImplementedError raise NotImplementedError
cpu_target = { cpu_target = {
"kasli": "or1k", "kasli": "riscv",
"kasli_soc": "cortexa9" "kasli_soc": "cortexa9"
}[description["target"]] }[description["target"]]

View File

@ -10,7 +10,7 @@ from collections import defaultdict
import h5py import h5py
from llvmlite_artiq import binding as llvm from llvmlite import binding as llvm
from sipyco import common_args from sipyco import common_args

View File

@ -37,7 +37,7 @@ mock_modules = ["artiq.gui.waitingspinnerwidget",
"qasync", "pyqtgraph", "matplotlib", "qasync", "pyqtgraph", "matplotlib",
"numpy", "dateutil", "dateutil.parser", "prettytable", "PyQt5", "numpy", "dateutil", "dateutil.parser", "prettytable", "PyQt5",
"h5py", "serial", "scipy", "scipy.interpolate", "h5py", "serial", "scipy", "scipy.interpolate",
"llvmlite_artiq", "Levenshtein", "pythonparser", "llvmlite", "Levenshtein", "pythonparser",
"sipyco", "sipyco.pc_rpc", "sipyco.sync_struct", "sipyco", "sipyco.pc_rpc", "sipyco.sync_struct",
"sipyco.asyncio_tools", "sipyco.logging_tools", "sipyco.asyncio_tools", "sipyco.logging_tools",
"sipyco.broadcast", "sipyco.packed_exceptions"] "sipyco.broadcast", "sipyco.packed_exceptions"]

View File

@ -15,7 +15,7 @@ requirements = [
"numpy", "scipy", "numpy", "scipy",
"python-dateutil", "prettytable", "h5py", "python-dateutil", "prettytable", "h5py",
"qasync", "pyqtgraph", "pygit2", "qasync", "pyqtgraph", "pygit2",
"llvmlite_artiq", "pythonparser", "python-Levenshtein", "llvmlite", "pythonparser", "python-Levenshtein",
] ]
console_scripts = [ console_scripts = [