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ad9154: adjust LMFCDel & LMFCVar based on DYN_LINK_LATENCY readbacks 

* @HarryMakes performed 25 consecutive power-cycles of Sayma, in 2-min intervals:
  * Results: MinDelay = 6, FALL_COUNT_Delay = 8 (w/ rollover)
This commit is contained in:
Harry Ho 2021-10-04 17:03:59 +08:00
parent 51e28de2f6
commit 412936f8db
1 changed files with 7 additions and 4 deletions
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11
artiq/firmware/libboard_artiq/ad9154.rs
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@ -324,10 +324,13 @@ pub fn setup(dacno: u8, linerate: u64) -> Result<(), &'static str> {
1*ad9154_reg::EQ_POWER_MODE); 1*ad9154_reg::EQ_POWER_MODE);
write(ad9154_reg::GENERAL_JRX_CTRL_1, 1); // subclass 1 write(ad9154_reg::GENERAL_JRX_CTRL_1, 1); // subclass 1
write(ad9154_reg::LMFC_DELAY_0, 0); // LMFCDel & LMFCVar were deduced from values of DYN_LINK_LATENCY_0
write(ad9154_reg::LMFC_DELAY_1, 0); // gathered from repeated power-cycles; see datasheet (Rev. C) p.44
write(ad9154_reg::LMFC_VAR_0, 0x0a); // receive buffer delay // "Link Delay Setup Example, Without Known Delay"
write(ad9154_reg::LMFC_VAR_1, 0x0a); write(ad9154_reg::LMFC_DELAY_0, 10);
write(ad9154_reg::LMFC_DELAY_1, 10);
write(ad9154_reg::LMFC_VAR_0, 4); // receive buffer delay
write(ad9154_reg::LMFC_VAR_1, 4);
write(ad9154_reg::SYNC_ERRWINDOW, 0); // +- 1/2 DAC clock write(ad9154_reg::SYNC_ERRWINDOW, 0); // +- 1/2 DAC clock
// datasheet seems to say ENABLE and ARM should be separate steps, // datasheet seems to say ENABLE and ARM should be separate steps,
// so enable now so it can be armed in sync(). // so enable now so it can be armed in sync().