occheung/artiq
1
0
Fork 0
forked from M-Labs/artiq
Code Pull Requests Activity

RELEASE_NOTES: fix formatting

Browse Source
This commit is contained in:
Sebastien Bourdeauducq 2023-01-19 16:42:52 +08:00
parent e9c65abebe
commit 3f5cc4aa10
1 changed files with 7 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
RELEASE_NOTES.rst
View File

@ -9,13 +9,13 @@ ARTIQ-8 (Unreleased)
Highlights:
* Hardware support:
- Implemented Phaser-servo. This requires recent gateware on Phaser.
- Implemented Phaser-MIQRO support. This requires the Phaser MIQRO gateware
variant.
- Sampler: fixed ADC MU to Volt conversion factor for Sampler v2.2+.
For earlier hardware versions, specify the hardware version in the device
database file (e.g. ``"hw_rev": "v2.1"``) to use the correct conversion factor.
- Metlino and Sayma support has been dropped due to complications with synchronous RTIO clocking.
- Implemented Phaser-servo. This requires recent gateware on Phaser.
- Implemented Phaser-MIQRO support. This requires the Phaser MIQRO gateware
variant.
- Sampler: fixed ADC MU to Volt conversion factor for Sampler v2.2+.
For earlier hardware versions, specify the hardware version in the device
database file (e.g. ``"hw_rev": "v2.1"``) to use the correct conversion factor.
- Metlino and Sayma support has been dropped due to complications with synchronous RTIO clocking.
* CPU (on softcore platforms) and AXI bus (on Zynq) are now clocked synchronously with the RTIO
clock, to facilitate implementation of local processing on DRTIO satellites, and to slightly
reduce RTIO latency.