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wrpll: fix mulshift

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This commit is contained in:
Sebastien Bourdeauducq 2020-10-16 22:05:20 +08:00
parent 90017da484
commit 3f076bf79b
1 changed files with 2 additions and 1 deletions
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3
artiq/gateware/drtio/wrpll/thls.py
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@ -552,7 +552,8 @@ class ProcessorImpl(Module):
if pd.multiplier_shifts:
if len(pd.multiplier_shifts) != 1:
raise NotImplementedError
multiplier = OpUnit(lambda a, b: a * b >> pd.multiplier_shifts[0],
# work around Migen's mishandling of Verilog's cretinous operator width rules
multiplier = OpUnit(lambda a, b: Cat(a, C(0, pd.data_width)) * Cat(b, C(0, pd.data_width)) >> pd.multiplier_shifts[0],
pd.data_width, pd.multiplier_stages)
else:
multiplier = NopUnit(pd.data_width)