style

2017-09-15 15:36:46 +08:00 · 2017-09-15 15:36:46 +08:00 · 3c922463a0
parent 8e5ab90129
commit 3c922463a0
1 changed files with 0 additions and 1 deletions
--- a/artiq/gateware/rtio/sed/tsc_gate.py
+++ b/artiq/gateware/rtio/sed/tsc_gate.py
@ -6,7 +6,6 @@ from artiq.gateware.rtio.sed import layouts
 __all__ = ["TSCGate"]


-
 class TSCGate(Module):
    def __init__(self, lane_count, seqn_width, layout_fifo_payload, layout_output_network_payload):
        self.input = [Record(layouts.fifo_egress(seqn_width, layout_fifo_payload))