forked from M-Labs/artiq
remove old examples
This commit is contained in:
parent
d8e1a22bdf
commit
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@ -1,231 +0,0 @@
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# Tester device database
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core_addr = "192.168.1.70"
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device_db = {
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"core": {
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"type": "local",
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"module": "artiq.coredevice.core",
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"class": "Core",
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"arguments": {"host": core_addr, "ref_period": 1e-9}
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},
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"core_log": {
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"type": "controller",
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"host": "::1",
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"port": 1068,
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"command": "aqctl_corelog -p {port} --bind {bind} " + core_addr
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},
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"core_cache": {
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"type": "local",
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"module": "artiq.coredevice.cache",
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"class": "CoreCache"
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},
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"core_dma": {
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"type": "local",
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"module": "artiq.coredevice.dma",
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"class": "CoreDMA"
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},
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"i2c_switch0": {
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"type": "local",
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"module": "artiq.coredevice.i2c",
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"class": "PCA9548",
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"arguments": {"address": 0xe0}
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},
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"i2c_switch1": {
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"type": "local",
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"module": "artiq.coredevice.i2c",
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"class": "PCA9548",
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"arguments": {"address": 0xe2}
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},
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}
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# DIO (EEM5) starting at RTIO channel 0
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for i in range(8):
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device_db["ttl" + str(i)] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLInOut" if i < 4 else "TTLOut",
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"arguments": {"channel": i},
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}
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device_db["ttl{}_counter".format(i)] = {
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"type": "local",
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"module": "artiq.coredevice.edge_counter",
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"class": "EdgeCounter",
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"arguments": {"channel": 8 + i},
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}
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# Urukul (EEM1) starting at RTIO channel 12
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device_db.update(
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eeprom_urukul0={
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"type": "local",
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"module": "artiq.coredevice.kasli_i2c",
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"class": "KasliEEPROM",
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"arguments": {"port": "EEM1"}
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},
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spi_urukul0={
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"type": "local",
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"module": "artiq.coredevice.spi2",
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"class": "SPIMaster",
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"arguments": {"channel": 12}
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},
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ttl_urukul0_sync={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLClockGen",
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"arguments": {"channel": 13, "acc_width": 4}
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},
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ttl_urukul0_io_update={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 14}
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},
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ttl_urukul0_sw0={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 15}
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},
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ttl_urukul0_sw1={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 16}
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},
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ttl_urukul0_sw2={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 17}
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},
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ttl_urukul0_sw3={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 18}
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},
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urukul0_cpld={
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"type": "local",
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"module": "artiq.coredevice.urukul",
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"class": "CPLD",
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"arguments": {
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"spi_device": "spi_urukul0",
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"io_update_device": "ttl_urukul0_io_update",
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"sync_device": "ttl_urukul0_sync",
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"refclk": 125e6,
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"clk_sel": 2
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}
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}
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)
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for i in range(4):
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device_db["urukul0_ch" + str(i)] = {
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"type": "local",
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"module": "artiq.coredevice.ad9910",
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"class": "AD9910",
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"arguments": {
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"pll_n": 32,
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"chip_select": 4 + i,
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"cpld_device": "urukul0_cpld",
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"sw_device": "ttl_urukul0_sw" + str(i),
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"sync_delay_seed": "eeprom_urukul0:" + str(64 + 4*i),
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"io_update_delay": "eeprom_urukul0:" + str(64 + 4*i),
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}
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}
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# Sampler (EEM3) starting at RTIO channel 19
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device_db["spi_sampler0_adc"] = {
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"type": "local",
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"module": "artiq.coredevice.spi2",
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"class": "SPIMaster",
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"arguments": {"channel": 19}
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}
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device_db["spi_sampler0_pgia"] = {
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"type": "local",
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"module": "artiq.coredevice.spi2",
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"class": "SPIMaster",
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"arguments": {"channel": 20}
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}
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device_db["spi_sampler0_cnv"] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 21},
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}
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device_db["sampler0"] = {
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"type": "local",
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"module": "artiq.coredevice.sampler",
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"class": "Sampler",
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"arguments": {
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"spi_adc_device": "spi_sampler0_adc",
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"spi_pgia_device": "spi_sampler0_pgia",
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"cnv_device": "spi_sampler0_cnv"
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}
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}
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# Zotino (EEM4) starting at RTIO channel 22
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device_db["spi_zotino0"] = {
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"type": "local",
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"module": "artiq.coredevice.spi2",
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"class": "SPIMaster",
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"arguments": {"channel": 22}
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}
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device_db["ttl_zotino0_ldac"] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 23}
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}
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device_db["ttl_zotino0_clr"] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 24}
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}
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device_db["zotino0"] = {
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"type": "local",
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"module": "artiq.coredevice.zotino",
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"class": "Zotino",
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"arguments": {
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"spi_device": "spi_zotino0",
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"ldac_device": "ttl_zotino0_ldac",
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"clr_device": "ttl_zotino0_clr"
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}
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}
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device_db.update(
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led0={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 25}
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},
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led1={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 26}
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},
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)
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device_db.update(
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i2c_switch="i2c_switch0",
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ttl_out="ttl4",
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ttl_out_serdes="ttl4",
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loop_out="ttl4",
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loop_in="ttl0",
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loop_in_counter="ttl0_counter",
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# Urukul CPLD with sync and io_update, IFC MODE 0b1000
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urukul_cpld="urukul0_cpld",
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# Urukul AD9910 with switch TTL, internal 125 MHz MMCX connection
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urukul_ad9910="urukul0_ch0",
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)
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@ -1,21 +0,0 @@
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from artiq.experiment import *
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class IdleKernel(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.setattr_device("led0")
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@kernel
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def run(self):
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start_time = now_mu() + self.core.seconds_to_mu(500*ms)
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while self.core.get_rtio_counter_mu() < start_time:
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pass
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self.core.reset()
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while True:
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self.led0.pulse(250*ms)
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delay(125*ms)
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self.led0.pulse(125*ms)
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delay(125*ms)
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self.led0.pulse(125*ms)
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delay(250*ms)
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@ -1,34 +0,0 @@
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core_addr = "192.168.1.70"
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device_db = {
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"core": {
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"type": "local",
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"module": "artiq.coredevice.core",
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"class": "Core",
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"arguments": {"host": core_addr, "ref_period": 1/(8*150e6)}
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},
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"core_log": {
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"type": "controller",
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"host": "::1",
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"port": 1068,
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"command": "aqctl_corelog -p {port} --bind {bind} " + core_addr
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},
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"core_cache": {
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"type": "local",
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"module": "artiq.coredevice.cache",
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"class": "CoreCache"
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},
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"core_dma": {
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"type": "local",
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"module": "artiq.coredevice.dma",
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"class": "CoreDMA"
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},
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}
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for i in range(3):
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device_db["led" + str(i)] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": i << 16},
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}
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@ -1,16 +0,0 @@
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from artiq.experiment import *
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class Blink(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.leds = [self.get_device("led0"), self.get_device("led2")]
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@kernel
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def run(self):
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self.core.reset()
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while True:
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for led in self.leds:
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led.pulse(200*ms)
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delay(200*ms)
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@ -1,177 +0,0 @@
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core_addr = "192.168.1.70"
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device_db = {
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"core": {
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"type": "local",
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"module": "artiq.coredevice.core",
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"class": "Core",
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"arguments": {"host": core_addr, "ref_period": 1/(8*150e6)}
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},
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"core_log": {
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"type": "controller",
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"host": "::1",
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"port": 1068,
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"command": "aqctl_corelog -p {port} --bind {bind} " + core_addr
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},
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"core_cache": {
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"type": "local",
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"module": "artiq.coredevice.cache",
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"class": "CoreCache"
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},
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"core_dma": {
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"type": "local",
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"module": "artiq.coredevice.dma",
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"class": "CoreDMA"
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},
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}
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device_db.update(
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spi_urukul0={
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"type": "local",
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"module": "artiq.coredevice.spi2",
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"class": "SPIMaster",
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"arguments": {"channel": 0}
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},
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ttl_urukul0_io_update={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 1}
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},
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ttl_urukul0_sw0={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 2}
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},
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ttl_urukul0_sw1={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 3}
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},
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ttl_urukul0_sw2={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 4}
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},
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ttl_urukul0_sw3={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 5}
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},
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urukul0_cpld={
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"type": "local",
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"module": "artiq.coredevice.urukul",
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"class": "CPLD",
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"arguments": {
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"spi_device": "spi_urukul0",
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"io_update_device": "ttl_urukul0_io_update",
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"refclk": 150e6,
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"clk_sel": 2
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}
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}
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)
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for i in range(4):
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device_db["urukul0_ch" + str(i)] = {
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"type": "local",
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"module": "artiq.coredevice.ad9910",
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"class": "AD9910",
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"arguments": {
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"pll_n": 16, # 600MHz sample rate
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"pll_vco": 2,
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"chip_select": 4 + i,
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"cpld_device": "urukul0_cpld",
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"sw_device": "ttl_urukul0_sw" + str(i)
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}
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}
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"""
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artiq_route routing.bin init
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artiq_route routing.bin set 0 0
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artiq_route routing.bin set 1 1 0
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artiq_route routing.bin set 2 1 1 0
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artiq_route routing.bin set 3 2 0
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artiq_route routing.bin set 4 2 1 0
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artiq_coremgmt -D kasli config write -f routing_table routing.bin
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"""
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for sayma in range(2):
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amc_base = 0x010000 + sayma*0x020000
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rtm_base = 0x020000 + sayma*0x020000
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for i in range(4):
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device_db["led" + str(4*sayma+i)] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": amc_base + i}
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}
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for i in range(2):
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device_db["ttl_mcx" + str(2*sayma+i)] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLInOut",
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"arguments": {"channel": amc_base + 4 + i}
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}
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for i in range(8):
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device_db["sawg" + str(8*sayma+i)] = {
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"type": "local",
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"module": "artiq.coredevice.sawg",
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"class": "SAWG",
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"arguments": {"channel_base": amc_base + 6 + i*10, "parallelism": 4}
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}
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for basemod in range(2):
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for i in range(4):
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device_db["sawg_sw" + str(8*sayma+4*basemod+i)] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": rtm_base + basemod*9 + i}
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}
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att_idx = 2*sayma + basemod
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device_db["basemod_att_rst_n"+str(att_idx)] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": rtm_base + basemod*9 + 4}
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}
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device_db["basemod_att_clk"+str(att_idx)] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": rtm_base + basemod*9 + 5}
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}
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device_db["basemod_att_le"+str(att_idx)] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": rtm_base + basemod*9 + 6}
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}
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device_db["basemod_att_mosi"+str(att_idx)] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": rtm_base + basemod*9 + 7}
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}
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device_db["basemod_att_miso"+str(att_idx)] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLInOut",
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"arguments": {"channel": rtm_base + basemod*9 + 8}
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}
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device_db["basemod_att"+str(att_idx)] = {
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"type": "local",
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"module": "artiq.coredevice.basemod_att",
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"class": "BaseModAtt",
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"arguments": {
|
||||
"rst_n": "basemod_att_rst_n"+str(att_idx),
|
||||
"clk": "basemod_att_clk"+str(att_idx),
|
||||
"le": "basemod_att_le"+str(att_idx),
|
||||
"mosi": "basemod_att_mosi"+str(att_idx),
|
||||
"miso": "basemod_att_miso"+str(att_idx),
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,25 +0,0 @@
|
||||
from artiq.experiment import *
|
||||
|
||||
|
||||
class BaseMod(EnvExperiment):
|
||||
def build(self):
|
||||
self.setattr_device("core")
|
||||
self.basemods = [self.get_device("basemod_att0"), self.get_device("basemod_att1")]
|
||||
self.rfsws = [self.get_device("sawg_sw"+str(i)) for i in range(8)]
|
||||
|
||||
@kernel
|
||||
def run(self):
|
||||
self.core.reset()
|
||||
for basemod in self.basemods:
|
||||
self.core.break_realtime()
|
||||
delay(10*ms)
|
||||
basemod.reset()
|
||||
delay(10*ms)
|
||||
basemod.set(0.0, 0.0, 0.0, 0.0)
|
||||
delay(10*ms)
|
||||
print(basemod.get_mu())
|
||||
|
||||
self.core.break_realtime()
|
||||
for rfsw in self.rfsws:
|
||||
rfsw.on()
|
||||
delay(1*ms)
|
||||
@ -1,37 +0,0 @@
|
||||
from artiq.experiment import *
|
||||
|
||||
|
||||
class Sines2Sayma(EnvExperiment):
|
||||
def build(self):
|
||||
self.setattr_device("core")
|
||||
self.sawgs = [self.get_device("sawg"+str(i)) for i in range(16)]
|
||||
|
||||
@kernel
|
||||
def drtio_is_up(self):
|
||||
for i in range(5):
|
||||
if not self.core.get_rtio_destination_status(i):
|
||||
return False
|
||||
return True
|
||||
|
||||
@kernel
|
||||
def run(self):
|
||||
while True:
|
||||
print("waiting for DRTIO ready...")
|
||||
while not self.drtio_is_up():
|
||||
pass
|
||||
print("OK")
|
||||
|
||||
self.core.reset()
|
||||
|
||||
for sawg in self.sawgs:
|
||||
delay(1*ms)
|
||||
sawg.reset()
|
||||
|
||||
for sawg in self.sawgs:
|
||||
delay(1*ms)
|
||||
sawg.amplitude1.set(.4)
|
||||
# Do not use a sub-multiple of oscilloscope sample rates.
|
||||
sawg.frequency0.set(9*MHz)
|
||||
|
||||
while self.drtio_is_up():
|
||||
pass
|
||||
@ -1,89 +0,0 @@
|
||||
from artiq.experiment import *
|
||||
|
||||
|
||||
class SinesUrukulSayma(EnvExperiment):
|
||||
def build(self):
|
||||
self.setattr_device("core")
|
||||
self.setattr_device("urukul0_cpld")
|
||||
|
||||
# Urukul clock output syntonized to the RTIO clock.
|
||||
# Can be used as HMC830 reference on Sayma RTM.
|
||||
# When using this reference, Sayma must be recalibrated every time Urukul
|
||||
# is rebooted, as Urukul is not synchronized to the Kasli.
|
||||
self.urukul_hmc_ref = self.get_device("urukul0_ch3")
|
||||
|
||||
# Urukul measurement channels - compare with SAWG outputs.
|
||||
# When testing sync, do not reboot Urukul, as it is not
|
||||
# synchronized to the Kasli.
|
||||
self.urukul_meas = [self.get_device("urukul0_ch" + str(i)) for i in range(3)]
|
||||
# The same waveform is output on all first 4 SAWG channels (first DAC).
|
||||
self.sawgs = [self.get_device("sawg"+str(i)) for i in range(4)]
|
||||
self.basemod = self.get_device("basemod_att0")
|
||||
self.rfsws = [self.get_device("sawg_sw"+str(i)) for i in range(4)]
|
||||
|
||||
|
||||
# DRTIO destinations:
|
||||
# 0: local
|
||||
# 1: Sayma AMC
|
||||
# 2: Sayma RTM
|
||||
@kernel
|
||||
def drtio_is_up(self):
|
||||
for i in range(3):
|
||||
if not self.core.get_rtio_destination_status(i):
|
||||
return False
|
||||
return True
|
||||
|
||||
@kernel
|
||||
def run(self):
|
||||
f = 9*MHz
|
||||
dds_ftw = self.urukul_meas[0].frequency_to_ftw(f)
|
||||
sawg_ftw = self.sawgs[0].frequency0.to_mu(f)
|
||||
if dds_ftw != sawg_ftw:
|
||||
print("DDS and SAWG FTWs do not match:", dds_ftw, sawg_ftw)
|
||||
return
|
||||
|
||||
self.core.reset()
|
||||
self.urukul0_cpld.init()
|
||||
|
||||
delay(1*ms)
|
||||
self.urukul_hmc_ref.init()
|
||||
self.urukul_hmc_ref.set_mu(0x40000000, asf=self.urukul_hmc_ref.amplitude_to_asf(0.6))
|
||||
self.urukul_hmc_ref.set_att(6.)
|
||||
self.urukul_hmc_ref.sw.on()
|
||||
|
||||
for urukul_ch in self.urukul_meas:
|
||||
delay(1*ms)
|
||||
urukul_ch.init()
|
||||
urukul_ch.set_mu(dds_ftw, asf=urukul_ch.amplitude_to_asf(0.5))
|
||||
urukul_ch.set_att(6.)
|
||||
urukul_ch.sw.on()
|
||||
|
||||
while True:
|
||||
print("waiting for DRTIO ready...")
|
||||
while not self.drtio_is_up():
|
||||
pass
|
||||
print("OK")
|
||||
|
||||
self.core.reset()
|
||||
|
||||
delay(10*ms)
|
||||
self.basemod.reset()
|
||||
delay(10*ms)
|
||||
self.basemod.set(3.0, 3.0, 3.0, 3.0)
|
||||
delay(10*ms)
|
||||
for rfsw in self.rfsws:
|
||||
delay(1*ms)
|
||||
rfsw.on()
|
||||
|
||||
for sawg in self.sawgs:
|
||||
delay(1*ms)
|
||||
sawg.reset()
|
||||
|
||||
for sawg in self.sawgs:
|
||||
delay(1*ms)
|
||||
sawg.amplitude1.set(.4)
|
||||
sawg.frequency0.set_mu(sawg_ftw)
|
||||
sawg.phase0.set_mu(sawg_ftw*now_mu() >> 17)
|
||||
|
||||
while self.drtio_is_up():
|
||||
pass
|
||||
@ -1,95 +0,0 @@
|
||||
core_addr = "192.168.1.65"
|
||||
|
||||
device_db = {
|
||||
"core": {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.core",
|
||||
"class": "Core",
|
||||
"arguments": {"host": core_addr, "ref_period": 1/(8*150e6)}
|
||||
},
|
||||
"core_log": {
|
||||
"type": "controller",
|
||||
"host": "::1",
|
||||
"port": 1068,
|
||||
"command": "aqctl_corelog -p {port} --bind {bind} " + core_addr
|
||||
},
|
||||
"core_cache": {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.cache",
|
||||
"class": "CoreCache"
|
||||
},
|
||||
"core_dma": {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.dma",
|
||||
"class": "CoreDMA"
|
||||
}
|
||||
}
|
||||
|
||||
# master peripherals
|
||||
for i in range(4):
|
||||
device_db["led" + str(i)] = {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.ttl",
|
||||
"class": "TTLOut",
|
||||
"arguments": {"channel": i},
|
||||
}
|
||||
|
||||
# DEST#1 peripherals
|
||||
amc_base = 0x070000
|
||||
rtm_base = 0x020000
|
||||
|
||||
for i in range(4):
|
||||
device_db["led" + str(4+i)] = {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.ttl",
|
||||
"class": "TTLOut",
|
||||
"arguments": {"channel": amc_base + i},
|
||||
}
|
||||
|
||||
#DIO (EEM0) starting at RTIO channel 0x000056
|
||||
for i in range(8):
|
||||
device_db["ttl" + str(i)] = {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.ttl",
|
||||
"class": "TTLOut",
|
||||
"arguments": {"channel": amc_base + 0x000056 + i},
|
||||
}
|
||||
|
||||
#DIO (EEM1) starting at RTIO channel 0x00005e
|
||||
for i in range(8):
|
||||
device_db["ttl" + str(8+i)] = {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.ttl",
|
||||
"class": "TTLOut",
|
||||
"arguments": {"channel": amc_base + 0x00005e + i},
|
||||
}
|
||||
|
||||
device_db["fmcdio_dirctl_clk"] = {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.ttl",
|
||||
"class": "TTLOut",
|
||||
"arguments": {"channel": amc_base + 0x000066}
|
||||
}
|
||||
|
||||
device_db["fmcdio_dirctl_ser"] = {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.ttl",
|
||||
"class": "TTLOut",
|
||||
"arguments": {"channel": amc_base + 0x000067}
|
||||
}
|
||||
|
||||
device_db["fmcdio_dirctl_latch"] = {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.ttl",
|
||||
"class": "TTLOut",
|
||||
"arguments": {"channel": amc_base + 0x000068}
|
||||
}
|
||||
|
||||
device_db["fmcdio_dirctl"] = {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.shiftreg",
|
||||
"class": "ShiftReg",
|
||||
"arguments": {"clk": "fmcdio_dirctl_clk",
|
||||
"ser": "fmcdio_dirctl_ser",
|
||||
"latch": "fmcdio_dirctl_latch"}
|
||||
}
|
||||
@ -1,129 +0,0 @@
|
||||
import sys
|
||||
import os
|
||||
import select
|
||||
|
||||
from artiq.experiment import *
|
||||
from artiq.coredevice.fmcdio_vhdci_eem import *
|
||||
|
||||
|
||||
def chunker(seq, size):
|
||||
res = []
|
||||
for el in seq:
|
||||
res.append(el)
|
||||
if len(res) == size:
|
||||
yield res
|
||||
res = []
|
||||
if res:
|
||||
yield res
|
||||
|
||||
|
||||
def is_enter_pressed() -> TBool:
|
||||
if os.name == "nt":
|
||||
if msvcrt.kbhit() and msvcrt.getch() == b"\r":
|
||||
return True
|
||||
else:
|
||||
return False
|
||||
else:
|
||||
if select.select([sys.stdin, ], [], [], 0.0)[0]:
|
||||
sys.stdin.read(1)
|
||||
return True
|
||||
else:
|
||||
return False
|
||||
|
||||
|
||||
class Demo(EnvExperiment):
|
||||
def build(self):
|
||||
self.setattr_device("core")
|
||||
self.setattr_device("fmcdio_dirctl")
|
||||
|
||||
self.leds = dict()
|
||||
self.ttl_outs = dict()
|
||||
|
||||
ddb = self.get_device_db()
|
||||
for name, desc in ddb.items():
|
||||
if isinstance(desc, dict) and desc["type"] == "local":
|
||||
module, cls = desc["module"], desc["class"]
|
||||
if (module, cls) == ("artiq.coredevice.ttl", "TTLOut"):
|
||||
dev = self.get_device(name)
|
||||
if "led" in name: # guess
|
||||
self.leds[name] = dev
|
||||
elif "ttl" in name: # to exclude fmcdio_dirctl
|
||||
self.ttl_outs[name] = dev
|
||||
|
||||
self.leds = sorted(self.leds.items(), key=lambda x: x[1].channel)
|
||||
self.ttl_outs = sorted(self.ttl_outs.items(), key=lambda x: x[1].channel)
|
||||
|
||||
self.dirctl_word = (
|
||||
shiftreg_bits(0, dio_bank0_out_pins | dio_bank1_out_pins) |
|
||||
shiftreg_bits(1, dio_bank0_out_pins | dio_bank1_out_pins)
|
||||
)
|
||||
|
||||
@kernel
|
||||
def init(self):
|
||||
self.core.break_realtime()
|
||||
print("*** Waiting for DRTIO ready...")
|
||||
drtio_indices = [7]
|
||||
for i in drtio_indices:
|
||||
while not self.drtio_is_up(i):
|
||||
pass
|
||||
|
||||
self.fmcdio_dirctl.set(self.dirctl_word)
|
||||
|
||||
@kernel
|
||||
def drtio_is_up(self, drtio_index):
|
||||
if not self.core.get_rtio_destination_status(drtio_index):
|
||||
return False
|
||||
print("DRTIO #", drtio_index, "is ready\n")
|
||||
return True
|
||||
|
||||
@kernel
|
||||
def test_led(self, led):
|
||||
while not is_enter_pressed():
|
||||
self.core.break_realtime()
|
||||
# do not fill the FIFOs too much to avoid long response times
|
||||
t = now_mu() - self.core.seconds_to_mu(0.2)
|
||||
while self.core.get_rtio_counter_mu() < t:
|
||||
pass
|
||||
for i in range(3):
|
||||
led.pulse(100*ms)
|
||||
delay(100*ms)
|
||||
|
||||
def test_leds(self):
|
||||
print("*** Testing LEDs.")
|
||||
print("Check for blinking. Press ENTER when done.")
|
||||
|
||||
for led_name, led_dev in self.leds:
|
||||
print("Testing LED: {}".format(led_name))
|
||||
self.test_led(led_dev)
|
||||
|
||||
@kernel
|
||||
def test_ttl_out_chunk(self, ttl_chunk):
|
||||
while not is_enter_pressed():
|
||||
self.core.break_realtime()
|
||||
for _ in range(50000):
|
||||
i = 0
|
||||
for ttl in ttl_chunk:
|
||||
i += 1
|
||||
for _ in range(i):
|
||||
ttl.pulse(1*us)
|
||||
delay(1*us)
|
||||
delay(10*us)
|
||||
|
||||
def test_ttl_outs(self):
|
||||
print("*** Testing TTL outputs.")
|
||||
print("Outputs are tested in groups of 4. Touch each TTL connector")
|
||||
print("with the oscilloscope probe tip, and check that the number of")
|
||||
print("pulses corresponds to its number in the group.")
|
||||
print("Press ENTER when done.")
|
||||
|
||||
for ttl_chunk in chunker(self.ttl_outs, 4):
|
||||
print("Testing TTL outputs: {}.".format(", ".join(name for name, dev in ttl_chunk)))
|
||||
self.test_ttl_out_chunk([dev for name, dev in ttl_chunk])
|
||||
|
||||
def run(self):
|
||||
self.core.reset()
|
||||
|
||||
if self.leds:
|
||||
self.test_leds()
|
||||
if self.ttl_outs:
|
||||
self.test_ttl_outs()
|
||||
@ -1,166 +0,0 @@
|
||||
core_addr = "192.168.1.60"
|
||||
|
||||
device_db = {
|
||||
"core": {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.core",
|
||||
"class": "Core",
|
||||
"arguments": {"host": core_addr, "ref_period": 1/(8*150e6)}
|
||||
},
|
||||
"core_log": {
|
||||
"type": "controller",
|
||||
"host": "::1",
|
||||
"port": 1068,
|
||||
"command": "aqctl_corelog -p {port} --bind {bind} " + core_addr
|
||||
},
|
||||
"core_cache": {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.cache",
|
||||
"class": "CoreCache"
|
||||
},
|
||||
"core_dma": {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.dma",
|
||||
"class": "CoreDMA"
|
||||
},
|
||||
}
|
||||
|
||||
for i in range(4):
|
||||
device_db["led" + str(i)] = {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.ttl",
|
||||
"class": "TTLOut",
|
||||
"arguments": {"channel": i},
|
||||
}
|
||||
|
||||
|
||||
for i in range(2):
|
||||
device_db["ttl" + str(i)] = {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.ttl",
|
||||
"class": "TTLInOut",
|
||||
"arguments": {"channel": 4 + i},
|
||||
}
|
||||
|
||||
|
||||
device_db.update(
|
||||
fmcdio_dirctl_clk={
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.ttl",
|
||||
"class": "TTLOut",
|
||||
"arguments": {"channel": 6}
|
||||
},
|
||||
fmcdio_dirctl_ser={
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.ttl",
|
||||
"class": "TTLOut",
|
||||
"arguments": {"channel": 7}
|
||||
},
|
||||
fmcdio_dirctl_latch={
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.ttl",
|
||||
"class": "TTLOut",
|
||||
"arguments": {"channel": 8}
|
||||
},
|
||||
fmcdio_dirctl={
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.shiftreg",
|
||||
"class": "ShiftReg",
|
||||
"arguments": {"clk": "fmcdio_dirctl_clk",
|
||||
"ser": "fmcdio_dirctl_ser",
|
||||
"latch": "fmcdio_dirctl_latch"}
|
||||
}
|
||||
)
|
||||
|
||||
device_db.update(
|
||||
spi_urukul0={
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.spi2",
|
||||
"class": "SPIMaster",
|
||||
"arguments": {"channel": 17}
|
||||
},
|
||||
ttl_urukul0_io_update={
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.ttl",
|
||||
"class": "TTLOut",
|
||||
"arguments": {"channel": 18}
|
||||
},
|
||||
ttl_urukul0_sw0={
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.ttl",
|
||||
"class": "TTLOut",
|
||||
"arguments": {"channel": 19}
|
||||
},
|
||||
ttl_urukul0_sw1={
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.ttl",
|
||||
"class": "TTLOut",
|
||||
"arguments": {"channel": 20}
|
||||
},
|
||||
ttl_urukul0_sw2={
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.ttl",
|
||||
"class": "TTLOut",
|
||||
"arguments": {"channel": 21}
|
||||
},
|
||||
ttl_urukul0_sw3={
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.ttl",
|
||||
"class": "TTLOut",
|
||||
"arguments": {"channel": 22}
|
||||
},
|
||||
urukul0_cpld={
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.urukul",
|
||||
"class": "CPLD",
|
||||
"arguments": {
|
||||
"spi_device": "spi_urukul0",
|
||||
"io_update_device": "ttl_urukul0_io_update",
|
||||
"refclk": 125e6,
|
||||
"clk_sel": 0
|
||||
}
|
||||
}
|
||||
)
|
||||
|
||||
for i in range(4):
|
||||
device_db["urukul0_ch" + str(i)] = {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.ad9910",
|
||||
"class": "AD9910",
|
||||
"arguments": {
|
||||
"pll_n": 32,
|
||||
"chip_select": 4 + i,
|
||||
"cpld_device": "urukul0_cpld",
|
||||
"sw_device": "ttl_urukul0_sw" + str(i)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
device_db["spi_zotino0"] = {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.spi2",
|
||||
"class": "SPIMaster",
|
||||
"arguments": {"channel": 23}
|
||||
}
|
||||
device_db["ttl_zotino0_ldac"] = {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.ttl",
|
||||
"class": "TTLOut",
|
||||
"arguments": {"channel": 24}
|
||||
}
|
||||
device_db["ttl_zotino0_clr"] = {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.ttl",
|
||||
"class": "TTLOut",
|
||||
"arguments": {"channel": 25}
|
||||
}
|
||||
device_db["zotino0"] = {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.zotino",
|
||||
"class": "Zotino",
|
||||
"arguments": {
|
||||
"spi_device": "spi_zotino0",
|
||||
"ldac_device": "ttl_zotino0_ldac",
|
||||
"clr_device": "ttl_zotino0_clr"
|
||||
}
|
||||
}
|
||||
@ -1,41 +0,0 @@
|
||||
from artiq.experiment import *
|
||||
from artiq.coredevice.fmcdio_vhdci_eem import *
|
||||
|
||||
|
||||
class Demo(EnvExperiment):
|
||||
def build(self):
|
||||
self.setattr_device("core")
|
||||
self.setattr_device("fmcdio_dirctl")
|
||||
|
||||
self.ttls = [self.get_device("ttl" + str(i)) for i in range(8)]
|
||||
self.setattr_device("urukul0_cpld")
|
||||
self.urukul_chs = [self.get_device("urukul0_ch" + str(i)) for i in range(4)]
|
||||
self.setattr_device("zotino0")
|
||||
|
||||
self.dirctl_word = (
|
||||
shiftreg_bits(1, urukul_out_pins) |
|
||||
shiftreg_bits(0, urukul_aux_out_pins) |
|
||||
shiftreg_bits(2, dio_bank0_out_pins | dio_bank1_out_pins) |
|
||||
shiftreg_bits(3, zotino_out_pins))
|
||||
|
||||
@kernel
|
||||
def run(self):
|
||||
self.core.reset()
|
||||
delay(10*ms)
|
||||
self.fmcdio_dirctl.set(self.dirctl_word)
|
||||
delay(10*ms)
|
||||
|
||||
self.urukul0_cpld.init()
|
||||
delay(10*ms)
|
||||
|
||||
self.zotino0.init()
|
||||
delay(1*ms)
|
||||
for i in range(32):
|
||||
self.zotino0.write_dac(i, i/4)
|
||||
delay(1*ms)
|
||||
|
||||
while True:
|
||||
for ttl in self.ttls:
|
||||
ttl.pulse(100*ms)
|
||||
for urukul_ch in self.urukul_chs:
|
||||
urukul_ch.sw.pulse(100*ms)
|
||||
Loading…
Reference in New Issue
Block a user