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Fix typos.

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Reduce ififo depth to 4 for Zotino.
This commit is contained in:
Thomas Harty 2018-03-19 09:42:18 +00:00
parent c4fa44bc62
commit 37d431039d
1 changed files with 3 additions and 3 deletions
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4
artiq/gateware/targets/kasli.py
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@ -357,7 +357,7 @@ class Opticlock(_StandaloneBase):
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
# EEM3 + EEM5: Urukul
# EEM5 + EEM4: Urukul
phy = spi2.SPIMaster(self.platform.request("eem5_spi_p"),
self.platform.request("eem5_spi_n"))
self.submodules += phy
@ -397,7 +397,7 @@ class Opticlock(_StandaloneBase):
phy = spi2.SPIMaster(self.platform.request("eem7_spi_p"),
self.platform.request("eem7_spi_n"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=16))
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
for signal in "ldac_n clr_n".split():
pads = platform.request("eem7_{}".format(signal))