forked from M-Labs/artiq
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91a4a7b0ee
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37a0d6580b
211
artiq/coredevice/spi2.py
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211
artiq/coredevice/spi2.py
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"""
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Driver for generic SPI on RTIO.
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This ARTIQ coredevice driver corresponds to the "new" MiSoC SPI core (v2).
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Output event replacement is not supported and issuing commands at the same
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time is an error.
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"""
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from numpy import int64
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from artiq.language.core import syscall, kernel, portable, now_mu, delay_mu
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from artiq.language.types import TInt32, TNone
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from artiq.coredevice.rtio import rtio_output, rtio_input_data
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__all__ = [
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"SPI_DATA_ADDR", "SPI_CONFIG_ADDR",
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"SPI_OFFLINE", "SPI_END", "SPI_INPUT",
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"SPI_CS_POLARITY", "SPI_CLK_POLARITY", "SPI_CLK_PHASE",
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"SPI_LSB_FIRST", "SPI_HALF_DUPLEX",
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"SPIMaster", "NRTSPIMaster"
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]
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SPI_DATA_ADDR = 0
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SPI_CONFIG_ADDR = 1
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SPI_OFFLINE = 0x01
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SPI_END = 0x02
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SPI_INPUT = 0x04
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SPI_CS_POLARITY = 0x08
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SPI_CLK_POLARITY = 0x10
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SPI_CLK_PHASE = 0x20
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SPI_LSB_FIRST = 0x40
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SPI_HALF_DUPLEX = 0x80
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class SPIMaster:
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"""Core device Serial Peripheral Interface (SPI) bus master.
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Owns one SPI bus.
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This ARTIQ coredevice driver corresponds to the "new" MiSoC SPI core (v2).
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**Transfer Sequence**:
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* If necessary, set the ``config`` register (:meth:`set_config` and
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:meth:`set_config_mu`) to activate and configure the core and to set
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various transfer parameters like transfer length, clock divider,
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and chip selects.
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* :meth:`write` to the ``data`` register. Writing starts the transfer.
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* If the transfer included submitting the SPI input data as an RTIO input
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event (``SPI_INPUT`` set), then :meth:`read` the ``data``.
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* If ``SPI_END`` was not set, repeat the transfer sequence.
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A **transaction** consists of one or more **transfers**. The chip select
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pattern is asserted for the entire length of the transaction. All but the
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last transfer are submitted with ``SPI_END`` cleared in the configuration
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register.
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:param channel: RTIO channel number of the SPI bus to control.
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"""
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kernel_invariants = {"core", "ref_period_mu", "channel"}
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def __init__(self, dmgr, channel, core_device="core"):
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self.core = dmgr.get(core_device)
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self.ref_period_mu = self.core.seconds_to_mu(
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self.core.coarse_ref_period)
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assert self.ref_period_mu == self.core.ref_multiplier
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self.channel = channel
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self.xfer_duration_mu = 2*self.ref_period_mu
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@portable
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def frequency_to_div(self, f):
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"""Convert a SPI clock frequency to the closest SPI clock divider."""
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return int64(round(
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1/(f*self.core.mu_to_seconds(self.ref_period_mu))))
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@kernel
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def set_config(self, flags, length, freq, c):
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"""Set the configuration register.
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* If ``SPI_CS_POLARITY`` is cleared (``cs`` active low, the default),
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"``cs`` all deasserted" means "all ``cs_n`` bits high".
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* ``cs_n`` is not mandatory in the pads supplied to the gateware core.
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Framing and chip selection can also be handled independently
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through other means, e.g. ``TTLOut``.
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* If there is a ``miso`` wire in the pads supplied in the gateware,
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input and output may be two signals ("4-wire SPI"),
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otherwise ``mosi`` must be used for both output and input
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("3-wire SPI") and ``SPI_HALF_DUPLEX`` must to be set
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when reading data or when the slave drives the
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``mosi`` signal at any point.
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* The first bit output on ``mosi`` is always the MSB/LSB (depending
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on ``SPI_LSB_FIRST``) of the ``data`` written, independent of
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the ``length`` of the transfer. The last bit input from ``miso``
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always ends up in the LSB/MSB (respectively) of the ``data`` read,
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independent of the ``length`` of the transfer.
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* ``cs`` is asserted at the beginning and deasserted at the end
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of the transaction.
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* ``cs`` handling is agnostic to whether it is one-hot or decoded
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somewhere downstream. If it is decoded, "``cs`` all deasserted"
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should be handled accordingly (no slave selected).
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If it is one-hot, asserting multiple slaves should only be attempted
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if ``miso`` is either not connected between slaves, or open
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collector, or correctly multiplexed externally.
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* Changes to the configuration register take effect on the start of the
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next transfer with the exception of ``SPI_OFFLINE`` which takes
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effect immediately.
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* The SPI core can only be written to when it is idle or waiting
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for the next transfer data. Writing (:meth:`set_config`,
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:meth:`set_config_mu` or :meth:`write`)
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when the core is busy will result in an RTIO busy error being logged.
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This method advances the timeline by one coarse RTIO clock cycle.
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**Configuration flags**:
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* :const:`SPI_OFFLINE`: all pins high-z (reset=1)
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* :const:`SPI_END`: transfer in progress (reset=1)
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* :const:`SPI_INPUT`: submit SPI read data as RTIO input event when
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transfer is complete (reset=0)
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* :const:`SPI_CS_POLARITY`: active level of ``cs_n`` (reset=0)
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* :const:`SPI_CLK_POLARITY`: idle level of ``clk`` (reset=0)
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* :const:`SPI_CLK_PHASE`: first edge after ``cs`` assertion to sample
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data on (reset=0). In Motorola/Freescale SPI language
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(:const:`SPI_CLK_POLARITY`, :const:`SPI_CLK_PHASE`) == (CPOL, CPHA):
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- (0, 0): idle low, output on falling, input on rising
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- (0, 1): idle low, output on rising, input on falling
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- (1, 0): idle high, output on rising, input on falling
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- (1, 1): idle high, output on falling, input on rising
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* :const:`SPI_LSB_FIRST`: LSB is the first bit on the wire (reset=0)
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* :const:`SPI_HALF_DUPLEX`: 3-wire SPI, in/out on ``mosi`` (reset=0)
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:param flags: A bit map of `SPI_*` flags.
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:param length: Number of bits to write during the next transfer.
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(reset=1)
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:param freq: Desired SPI clock frequency. (reset=f_rtio/2)
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:param cs: Bit pattern of chip selects to assert.
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Or number of the chip select to assert if ``cs`` is decoded
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downstream. (reset=0)
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"""
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self.set_config_mu(
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flags, length, self.frequency_to_div(write_freq), cs)
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@kernel
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def set_config_mu(self, flags, length, div, cs):
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"""Set the ``config`` register (in SPI bus machine units).
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.. seealso:: :meth:`set_config`
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:param flags: A bit map of `SPI_*` flags.
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:param length: Number of bits to write during the next transfer.
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(reset=1)
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:param div: Counter load value to divide the RTIO
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clock by to generate the SPI clock. (minimum=2, reset=2)
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``f_rtio_clk/f_spi == div``. If ``div`` is odd,
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the setup phase of the SPI clock is one coarse RTIO clock cycle
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longer than the hold phase.
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:param cs: Bit pattern of chip selects to assert.
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Or number of the chip select to assert if ``cs`` is decoded
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downstream. (reset=0)
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"""
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if length > 32 or length < 1:
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raise ValueError("Invalid SPI transfer length")
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if div > 257 or div < 2:
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raise ValueError("Invalid SPI clock divider")
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self.xfer_duration_mu = (length + 1)*div*self.ref_period_mu
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rtio_output(now_mu(), self.channel, SPI_CONFIG_ADDR, flags |
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((length - 1) << 8) | ((div - 2) << 16) | (cs << 24))
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delay_mu(self.ref_period_mu)
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@kernel
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def write(self, data):
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"""Write SPI data to shift register register and start transfer.
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* The ``data`` register and the shift register are 32 bits wide.
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* Data writes take one ``ref_period`` cycle.
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* A transaction consisting of a single transfer (``SPI_END``) takes
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:attr:`xfer_duration_mu` ``=(n + 1)*div`` cycles RTIO time where
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``n`` is the number of bits and ``div`` is the SPI clock divider.
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* Transfers in a multi-transfer transaction take up to one SPI clock
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cycle less time depending on multiple parameters. Advanced users may
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rewind the timeline appropriately to achieve faster multi-transfer
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transactions.
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* The SPI core will be busy for the duration of the SPI transfer.
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* For bit alignment and bit ordering see :meth:`set_config`.
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* The SPI core can only be written to when it is idle or waiting
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for the next transfer data. Writing (:meth:`set_config`,
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:meth:`set_config_mu` or :meth:`write`)
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when the core is busy will result in an RTIO busy error being logged.
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This method advances the timeline by the duration of one
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single-transfer SPI transaction (:attr:`xfer_duration_mu`).
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:param data: SPI output data to be written.
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"""
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rtio_output(now_mu(), self.channel, SPI_DATA_ADDR, data)
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delay_mu(self.xfer_duration_mu)
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@kernel
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def read(self):
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"""Read SPI data submitted by the SPI core.
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For bit alignment and bit ordering see :meth:`set_config`.
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This method does not alter the timeline.
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:return: SPI input data.
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"""
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return rtio_input_data(self.channel)
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116
artiq/gateware/rtio/phy/spi2.py
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116
artiq/gateware/rtio/phy/spi2.py
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from migen import *
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from misoc.cores.spi2 import SPIMachine, SPIInterfaceXC7Diff, SPIInterface
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from artiq.gateware.rtio import rtlink
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class SPIMaster(Module):
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"""
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RTIO SPI Master version 2.
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Register address and bit map:
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data (address 0):
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32 write/read data
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config (address 1):
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1 offline: all pins high-z (reset=1)
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1 end: end transaction with next transfer (reset=1)
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1 input: submit read data on RTIO input when readable (reset=0)
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1 cs_polarity: active level of chip select (reset=0)
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1 clk_polarity: idle level of clk (reset=0)
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1 clk_phase: first edge after cs assertion to sample data on (reset=0)
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(clk_polarity, clk_phase) == (CPOL, CPHA) in Freescale language.
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(0, 0): idle low, output on falling, input on rising
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(0, 1): idle low, output on rising, input on falling
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(1, 0): idle high, output on rising, input on falling
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(1, 1): idle high, output on falling, input on rising
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There is never a clk edge during a cs edge.
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1 lsb_first: LSB is the first bit on the wire (reset=0)
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1 half_duplex: 3-wire SPI, in/out on mosi (reset=0)
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5 length: 1-32 bits = length + 1 (reset=0)
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3 padding
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8 div: counter load value to divide this module's clock
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to generate the SPI write clk (reset=0)
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f_clk/f_spi == div + 2
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8 cs: active high bit pattern of chip selects (reset=0)
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"""
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def __init__(self, pads, pads_n=None):
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to_rio_phy = ClockDomainsRenamer("rio_phy")
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if pads_n is None:
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interface = SPIInterface(pads)
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else:
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interface = SPIInterfaceXC7Diff(pads, pads_n)
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interface = to_rio_phy(interface)
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spi = to_rio_phy(SPIMachine(data_width=32, div_width=8))
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self.submodules += interface, spi
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self.rtlink = rtlink.Interface(
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rtlink.OInterface(len(spi.reg.pdo), address_width=1,
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enable_replace=False),
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rtlink.IInterface(len(spi.reg.pdi), timestamped=False)
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)
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###
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config = Record([
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("offline", 1),
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("end", 1),
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("input", 1),
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("cs_polarity", 1),
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("clk_polarity", 1),
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("clk_phase", 1),
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("lsb_first", 1),
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("half_duplex", 1),
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("length", 5),
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("padding", 3),
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("div", 8),
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("cs", 8),
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])
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assert len(config) == len(spi.reg.pdo) == len(spi.reg.pdi) == 32
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config.offline.reset = 1
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config.end.reset = 1
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read = Signal()
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self.sync.rio += [
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If(self.rtlink.i.stb,
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read.eq(0)
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),
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If(self.rtlink.o.stb & spi.writable,
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If(self.rtlink.o.address,
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config.raw_bits().eq(self.rtlink.o.data)
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).Else(
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read.eq(config.input)
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)
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),
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]
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self.comb += [
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spi.length.eq(config.length),
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spi.end.eq(config.end),
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spi.cg.div.eq(config.div),
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spi.clk_phase.eq(config.clk_phase),
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spi.reg.lsb_first.eq(config.lsb_first),
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interface.half_duplex.eq(config.half_duplex),
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interface.cs.eq(config.cs),
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interface.cs_polarity.eq(Replicate(
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config.cs_polarity, len(interface.cs_polarity))),
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interface.clk_polarity.eq(config.clk_polarity),
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interface.offline.eq(config.offline),
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interface.cs_next.eq(spi.cs_next),
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interface.clk_next.eq(spi.clk_next),
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interface.ce.eq(spi.ce),
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interface.sample.eq(spi.reg.sample),
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spi.reg.sdi.eq(interface.sdi),
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interface.sdo.eq(spi.reg.sdo),
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spi.load.eq(self.rtlink.o.stb & spi.writable &
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~self.rtlink.o.address),
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spi.reg.pdo.eq(self.rtlink.o.data),
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self.rtlink.o.busy.eq(~spi.writable),
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self.rtlink.i.stb.eq(spi.readable & read),
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self.rtlink.i.data.eq(spi.reg.pdi)
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]
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self.probes = []
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@ -15,7 +15,7 @@ requirements:
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- python >=3.5.3,<3.6
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- setuptools 33.1.1
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- migen 0.7 py35_4+git9c3a301
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- misoc 0.9 py35_10+git3072d794
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- misoc 0.9 py35_11+git10062189
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- jesd204b 0.4
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- microscope
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- binutils-or1k-linux >=2.27
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@ -33,6 +33,12 @@ These drivers are for the core device and the peripherals closely integrated int
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.. automodule:: artiq.coredevice.spi
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:members:
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:mod:`artiq.coredevice.spi2` module
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-----------------------------------
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.. automodule:: artiq.coredevice.spi2
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:members:
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:mod:`artiq.coredevice.ad5360` module
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-------------------------------------
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Loading…
Reference in New Issue
Block a user