Expose TTLClockGen for Kasli JSONs (#1886)

RELEASE_NOTES.rst

@@ -12,6 +12,7 @@ Highlights:
    - Kasli-SoC, a new EEM carrier based on a Zynq SoC, enabling much faster kernel execution.
    - HVAMP_8CH 8 channel HV amplifier for Fastino / Zotinos
    - Almazny mezzanine board for Mirny
+* TTL device output can be now configured to work as a clock generator.
 * Softcore targets now use the RISC-V architecture (VexRiscv) instead of OR1K (mor1kx).
 * Gateware FPU is supported on KC705 and Kasli 2.0.
 * Faster compilation for large arrays/lists.

artiq/coredevice/coredevice_generic.schema.json

@@ -170,11 +170,11 @@
                         },
                         "bank_direction_low": {
                             "type": "string",
-                            "enum": ["input", "output"]
+                            "enum": ["input", "output", "clkgen"]
                         },
                         "bank_direction_high": {
                             "type": "string",
-                            "enum": ["input", "output"]
+                            "enum": ["input", "output", "clkgen"]
                         }
                     },
                     "required": ["ports", "bank_direction_low", "bank_direction_high"]

artiq/frontend/artiq_ddb_template.py

@@ -94,7 +94,8 @@ class PeripheralManager:
     def process_dio(self, rtio_offset, peripheral, num_channels=8):
         class_names = {
             "input": "TTLInOut",
-            "output": "TTLOut"
+            "output": "TTLOut",
+            "clkgen": "TTLClockGen"
         }
         classes = [
             class_names[peripheral["bank_direction_low"]],

artiq/gateware/eem.py

@@ -231,10 +231,8 @@ class Urukul(_EEM):
         target.rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
 
         pads = target.platform.request("urukul{}_dds_reset_sync_in".format(eem))
-        pad = Signal(reset=0)
-        target.specials += DifferentialOutput(pad, pads.p, pads.n)
         if sync_gen_cls is not None:  # AD9910 variant and SYNC_IN from EEM
-            phy = sync_gen_cls(pad, ftw_width=4)
+            phy = sync_gen_cls(pad=pads.p, pad_n=pads.n, ftw_width=4)
             target.submodules += phy
             target.rtio_channels.append(rtio.Channel.from_phy(phy))
 

artiq/gateware/eem_7series.py

@@ -5,7 +5,8 @@ from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, edge_counter
 def peripheral_dio(module, peripheral, **kwargs):
     ttl_classes = {
         "input": ttl_serdes_7series.InOut_8X,
-        "output": ttl_serdes_7series.Output_8X
+        "output": ttl_serdes_7series.Output_8X,
+        "clkgen": ttl_simple.ClockGen
     }
     if len(peripheral["ports"]) != 1:
         raise ValueError("wrong number of ports")

artiq/gateware/rtio/phy/ttl_simple.py

@@ -145,11 +145,16 @@ class InOut(Module):
 
 
 class ClockGen(Module):
-    def __init__(self, pad, ftw_width=24):
+    def __init__(self, pad, pad_n=None, ftw_width=24, dci=False):
         self.rtlink = rtlink.Interface(rtlink.OInterface(ftw_width))
 
         # # #
 
+        pad_o = Signal()
+        if pad_n is None:
+            self.comb += pad.eq(pad_o)
+        else:
+            self.specials += DifferentialOutput(pad_o, pad, pad_n)
         ftw = Signal(ftw_width)
         acc = Signal(ftw_width)
         self.sync.rio += If(self.rtlink.o.stb, ftw.eq(self.rtlink.o.data))
@@ -165,5 +170,5 @@ class ClockGen(Module):
                     acc.eq(0)
                 )
             ),
-            pad.eq(acc[-1])
+            pad_o.eq(acc[-1])
         ]