occheung/artiq
1
0
Fork 0
forked from M-Labs/artiq
Code Pull Requests Activity

satman: wait for CPLL/QPLL lock after setting drtio_transceiver::stable_clkin

Browse Source
This commit is contained in:
Sebastien Bourdeauducq 2019-01-07 17:09:19 +08:00
parent 3217488824
commit 332bd6090f
1 changed files with 1 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
artiq/firmware/satman/main.rs
View File

@ -416,6 +416,7 @@ pub extern fn main() -> i32 {
unsafe {
csr::drtio_transceiver::stable_clkin_write(1);
}
clock::spin_us(1500); // wait for CPLL/QPLL lock
init_rtio_crg();
#[cfg(has_allaki_atts)]