occheung
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

kasli: default to 125MHz frequency for DRTIO 

This is the consistent and most common option. Sayma will also eventually move to it.
This commit is contained in:
Sebastien Bourdeauducq 2019-10-08 12:59:52 +08:00
parent 4df2c5d1fb
commit 314d9b5d06
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
artiq/gateware/targets/kasli.py
View File

@ -273,7 +273,7 @@ class MasterBase(MiniSoC, AMPSoC):
}
mem_map.update(MiniSoC.mem_map)
def __init__(self, rtio_clk_freq=150e6, enable_sata=False, **kwargs):
def __init__(self, rtio_clk_freq=125e6, enable_sata=False, **kwargs):
MiniSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
@ -435,7 +435,7 @@ class SatelliteBase(BaseSoC):
}
mem_map.update(BaseSoC.mem_map)
def __init__(self, rtio_clk_freq=150e6, enable_sata=False, **kwargs):
def __init__(self, rtio_clk_freq=125e6, enable_sata=False, **kwargs):
BaseSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",