Merge branch 'master' into nac3

artiq/coredevice/shuttler.py

@@ -111,7 +111,7 @@ class Config:
 
 
 @nac3
-class Volt:
+class DCBias:
     """Shuttler Core cubic DC-bias spline.
 
     A Shuttler channel can generate a waveform `w(t)` that is the sum of a
@@ -145,7 +145,7 @@ class Volt:
     def set_waveform(self, a0: int32, a1: int32, a2: int64, a3: int64):
         """Set the DC-bias spline waveform.
 
-        Given `a(t)` as defined in :class:`Volt`, the coefficients should be
+        Given `a(t)` as defined in :class:`DCBias`, the coefficients should be
         configured by the following formulae.
 
         .. math::
@@ -189,7 +189,7 @@ class Volt:
 
 
 @nac3
-class Dds:
+class DDS:
     """Shuttler Core DDS spline.
 
     A Shuttler channel can generate a waveform `w(t)` that is the sum of a
@@ -228,7 +228,7 @@ class Dds:
             c0: int32, c1: int32, c2: int32):
         """Set the DDS spline waveform.
 
-        Given `b(t)` and `c(t)` as defined in :class:`Dds`, the coefficients
+        Given `b(t)` and `c(t)` as defined in :class:`DDS`, the coefficients
         should be configured by the following formulae.
 
         .. math::
@@ -308,7 +308,7 @@ class Trigger:
 
         Each bit corresponds to a Shuttler waveform generator core. Setting
         `trig_out` bits commits the pending coefficient update (from
-        `set_waveform` in :class:`Volt` and :class:`Dds`) to the Shuttler Core
+        `set_waveform` in :class:`DCBias` and :class:`DDS`) to the Shuttler Core
         synchronously.
 
         :param trig_out: Coefficient update trigger bits. The MSB corresponds
@@ -580,7 +580,7 @@ class ADC:
         self.core.delay(2500.*us)
 
     @kernel
-    def calibrate(self, volts: list[Volt], trigger: Trigger, config: Config, samples: Option[list[float]] = none):
+    def calibrate(self, volts: list[DCBias], trigger: Trigger, config: Config, samples: Option[list[float]] = none):
         """Calibrate the Shuttler waveform generator using the ADC on the AFE.
 
         It finds the average slope rate and average offset by samples, and
@@ -599,7 +599,7 @@ class ADC:
             :meth:`Config.set_offset`
 
         :param volts: A list of all 16 cubic DC-bias spline.
-            (See :class:`Volt`)
+            (See :class:`DCBias`)
         :param trigger: The Shuttler spline coefficient update trigger.
         :param config: The Shuttler Core configuration registers.
         :param samples: A list of sample voltages for calibration. There must

artiq/examples/kasli_shuttler/kasli_shuttler.json

@@ -1,12 +1,12 @@
 {
     "target": "kasli",
-    "variant": "master",
+    "variant": "shuttlerdemo",
     "hw_rev": "v2.0",
-    "base": "master",
+    "drtio_role": "master",
     "peripherals": [
         {
             "type": "shuttler",
-                "ports": [0]
+            "ports": [0]
         },
         {
             "type": "dio",

artiq/examples/kasli_shuttler/repository/shuttler.py

@@ -7,8 +7,8 @@ from artiq.coredevice.shuttler import (
     shuttler_volt_to_mu,
     Config as ShuttlerConfig,
     Trigger as ShuttlerTrigger,
-    Volt as ShuttlerDCBias,
+    DCBias as ShuttlerDCBias,
-    Dds as ShuttlerDDS,
+    DDS as ShuttlerDDS,
     Relay as ShuttlerRelay,
     ADC as ShuttlerADC)
 
@@ -70,7 +70,7 @@ class Shuttler(EnvExperiment):
     shuttler0_leds: KernelInvariant[list[TTLOut]]
     shuttler0_config: KernelInvariant[ShuttlerConfig]
     shuttler0_trigger: KernelInvariant[ShuttlerTrigger]
-    shuttler0_volt: KernelInvariant[list[ShuttlerDCBias]]
+    shuttler0_dcbias: KernelInvariant[list[ShuttlerDCBias]]
     shuttler0_dds: KernelInvariant[list[ShuttlerDDS]]
     shuttler0_relay: KernelInvariant[ShuttlerRelay]
     shuttler0_adc: KernelInvariant[ShuttlerADC]
@@ -81,7 +81,7 @@ class Shuttler(EnvExperiment):
         self.shuttler0_leds = [ self.get_device("shuttler0_led{}".format(i)) for i in range(2) ]
         self.setattr_device("shuttler0_config")
         self.setattr_device("shuttler0_trigger")
-        self.shuttler0_volt = [ self.get_device("shuttler0_volt{}".format(i)) for i in range(16) ]
+        self.shuttler0_dcbias = [ self.get_device("shuttler0_dcbias{}".format(i)) for i in range(16) ]
         self.shuttler0_dds = [ self.get_device("shuttler0_dds{}".format(i)) for i in range(16) ]
         self.setattr_device("shuttler0_relay")
         self.setattr_device("shuttler0_adc")
@@ -114,7 +114,7 @@ class Shuttler(EnvExperiment):
 
     @kernel
     def shuttler_channel_reset(self, ch: int32):
-        self.shuttler0_volt[ch].set_waveform(
+        self.shuttler0_dcbias[ch].set_waveform(
             a0=0,
             a1=0,
             a2=int64(0),
@@ -238,7 +238,7 @@ class Shuttler(EnvExperiment):
         self.core.delay(500.*us)
 
         ## Step 5 ##
-        self.shuttler0_volt[0].set_waveform(
+        self.shuttler0_dcbias[0].set_waveform(
             a0=shuttler_volt_amp_mu(-5.0),
             a1=int32(shuttler_volt_damp_mu(0.01)),
             a2=int64(0),
@@ -253,7 +253,7 @@ class Shuttler(EnvExperiment):
             c1=shuttler_freq_mu(end_f_MHz),
             c2=0,
         )
-        self.shuttler0_volt[1].set_waveform(
+        self.shuttler0_dcbias[1].set_waveform(
             a0=shuttler_volt_amp_mu(-5.0),
             a1=int32(shuttler_volt_damp_mu(0.01)),
             a2=int64(0),
@@ -272,7 +272,7 @@ class Shuttler(EnvExperiment):
         self.core.delay(1000.*us)
         
         ## Step 6 ##
-        self.shuttler0_volt[0].set_waveform(
+        self.shuttler0_dcbias[0].set_waveform(
             a0=shuttler_volt_amp_mu(-2.5),
             a1=int32(shuttler_volt_damp_mu(0.01)),
             a2=int64(0),
@@ -292,7 +292,7 @@ class Shuttler(EnvExperiment):
         self.core.delay(500.*us)
 
         ## Step 7 ##
-        self.shuttler0_volt[0].set_waveform(
+        self.shuttler0_dcbias[0].set_waveform(
             a0=shuttler_volt_amp_mu(2.5),
             a1=int32(shuttler_volt_damp_mu(-0.01)),
             a2=int64(0),
@@ -339,4 +339,4 @@ class Shuttler(EnvExperiment):
         # The actual output voltage is limited by the hardware, the calculated calibration gain and offset.
         # For example, if the system has a calibration gain of 1.06, then the max output voltage = 10 / 1.06 = 9.43V.
         # Setting a value larger than 9.43V will result in overflow.
-        self.shuttler0_adc.calibrate(self.shuttler0_volt, self.shuttler0_trigger, self.shuttler0_config)
+        self.shuttler0_adc.calibrate(self.shuttler0_dcbias, self.shuttler0_trigger, self.shuttler0_config)

artiq/examples/nac3devices/nac3devices.py

@@ -14,7 +14,7 @@ from artiq.coredevice.edge_counter import EdgeCounter
 from artiq.coredevice.grabber import Grabber
 from artiq.coredevice.fastino import Fastino
 from artiq.coredevice.phaser import Phaser
-from artiq.coredevice.shuttler import Volt as ShuttlerDCBias, Dds as ShuttlerDDS
+from artiq.coredevice.shuttler import DCBias as ShuttlerDCBias, DDS as ShuttlerDDS
 
 
 @nac3
@@ -35,7 +35,7 @@ class NAC3Devices(EnvExperiment):
     grabber0: KernelInvariant[Grabber]
     fastino0: KernelInvariant[Fastino]
     phaser0: KernelInvariant[Phaser]
-    shuttler0_volt0: KernelInvariant[ShuttlerDCBias]
+    shuttler0_dcbias0: KernelInvariant[ShuttlerDCBias]
     shuttler0_dds0: KernelInvariant[ShuttlerDDS]
 
     def build(self):
@@ -55,7 +55,7 @@ class NAC3Devices(EnvExperiment):
         self.setattr_device("grabber0")
         self.setattr_device("fastino0")
         self.setattr_device("phaser0")
-        self.setattr_device("shuttler0_volt0")
+        self.setattr_device("shuttler0_dcbias0")
         self.setattr_device("shuttler0_dds0")
 
     @kernel

artiq/frontend/artiq_ddb_template.py

@@ -624,10 +624,10 @@ class PeripheralManager:
             channel=rtio_offset + next(channel))
         for i in range(16):
             self.gen("""
-                device_db["{name}_volt{ch}"] = {{
+                device_db["{name}_dcbias{ch}"] = {{
                     "type": "local",
                     "module": "artiq.coredevice.shuttler",
-                    "class": "Volt",
+                    "class": "DCBias",
                     "arguments": {{"channel": 0x{channel:06x}}},
                 }}""",
                 name=shuttler_name,
@@ -637,7 +637,7 @@ class PeripheralManager:
                 device_db["{name}_dds{ch}"] = {{
                     "type": "local",
                     "module": "artiq.coredevice.shuttler",
-                    "class": "Dds",
+                    "class": "DDS",
                     "arguments": {{"channel": 0x{channel:06x}}},
                 }}""",
                 name=shuttler_name,
@@ -729,16 +729,26 @@ def process(output, primary_description, satellites):
         peripherals, satellite_drtio_peripherals = split_drtio_eem(description["peripherals"])
         drtio_peripherals.extend(satellite_drtio_peripherals)
 
-        print("# DEST#{} peripherals".format(destination), file=output)
+        print(textwrap.dedent("""
-        print("device_db[\"satellite_cpu_targets\"][{}] = \"{}\"".format(destination, get_cpu_target(description)), file=output)
+            # DEST#{dest} peripherals
+
+            device_db["satellite_cpu_targets"][{dest}] = \"{target}\"""").format(
+                dest=destination,
+                target=get_cpu_target(description)),
+            file=output)
         rtio_offset = destination << 16
         for peripheral in peripherals:
             n_channels = pm.process(rtio_offset, peripheral)
             rtio_offset += n_channels
     
     for peripheral in drtio_peripherals:
-        print("# DEST#{} peripherals".format(peripheral["drtio_destination"]), file=output)
+        print(textwrap.dedent("""
-        print("device_db[\"satellite_cpu_targets\"][{}] = \"{}\"".format(peripheral["drtio_destination"], get_cpu_target(peripheral)), file=output)
+            # DEST#{dest} peripherals
+
+            device_db["satellite_cpu_targets"][{dest}] = \"{target}\"""").format(
+                dest=peripheral["drtio_destination"],
+                target=get_cpu_target(peripheral)),
+            file=output)
         processor = getattr(pm, "process_"+str(peripheral["type"]))
         processor(peripheral)