forked from M-Labs/artiq
kasli_sawgmaster: generate a HMC830 clock with Urukul
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@ -5,7 +5,20 @@ class SinesUrukulSayma(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.setattr_device("urukul0_cpld")
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self.urukul_chs = [self.get_device("urukul0_ch" + str(i)) for i in range(4)]
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# Urukul clock output syntonized to the RTIO clock.
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# Can be used as HMC830 reference on Sayma RTM.
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# The clock output on Sayma AMC cannot be used, as it is derived from
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# another Si5324 output than the GTH, and the two Si5324 output dividers
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# are not synchronized with each other.
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# When using this reference, Sayma must be recalibrated every time Urukul
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# is rebooted, as Urukul is not synchronized to the Kasli.
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self.urukul_hmc_ref = self.get_device("urukul0_ch3")
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# Urukul measurement channels - compare with SAWG outputs.
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# When testing sync, do not reboot Urukul, as it is not
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# synchronized to the Kasli.
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self.urukul_meas = [self.get_device("urukul0_ch" + str(i)) for i in range(3)]
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self.sawgs = [self.get_device("sawg"+str(i)) for i in range(8)]
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@kernel
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@ -18,17 +31,22 @@ class SinesUrukulSayma(EnvExperiment):
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@kernel
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def run(self):
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f = 9*MHz
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dds_ftw = self.urukul_chs[0].frequency_to_ftw(f)
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dds_ftw = self.urukul_meas[0].frequency_to_ftw(f)
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sawg_ftw = self.sawgs[0].frequency0.to_mu(f)
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if dds_ftw != sawg_ftw:
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print("DDS and SAWG FTWs do not match:", dds_ftw, sawg_ftw)
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return
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# Note: when testing sync, do not reboot Urukul, as it is not
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# synchronized to the FPGA (yet).
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self.core.reset()
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self.urukul0_cpld.init()
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for urukul_ch in self.urukul_chs:
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delay(1*ms)
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self.urukul_hmc_ref.init()
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self.urukul_hmc_ref.set_mu(0x40000000, asf=self.urukul_hmc_ref.amplitude_to_asf(0.6))
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self.urukul_hmc_ref.set_att(6.)
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self.urukul_hmc_ref.sw.on()
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for urukul_ch in self.urukul_meas:
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delay(1*ms)
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urukul_ch.init()
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urukul_ch.set_mu(dds_ftw, asf=urukul_ch.amplitude_to_asf(0.5))
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