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sayma_amc: remove RTM bitstream upload core. Closes #908

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Sebastien Bourdeauducq 2018-02-07 12:27:35 +08:00
parent 61c64a76be
commit 2d4a1340ea
1 changed files with 4 additions and 3 deletions
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7
artiq/gateware/targets/sayma_amc.py
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@ -160,9 +160,10 @@ class Standalone(MiniSoC, AMPSoC):
]
# RTM bitstream upload
rtm_fpga_cfg = platform.request("rtm_fpga_cfg")
self.submodules.rtm_fpga_cfg = SlaveFPGA(rtm_fpga_cfg)
self.csr_devices.append("rtm_fpga_cfg")
# https://github.com/m-labs/artiq/issues/908#issuecomment-363650534
#rtm_fpga_cfg = platform.request("rtm_fpga_cfg")
#self.submodules.rtm_fpga_cfg = SlaveFPGA(rtm_fpga_cfg)
#self.csr_devices.append("rtm_fpga_cfg")
# AMC/RTM serwb
serwb_pll = serwb.phy.SERWBPLL(125e6, 625e6, vco_div=2)