occheung
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

gateware: reset RTIO DMA core when kernel CPU is reset

This commit is contained in:
Sebastien Bourdeauducq 2017-03-31 15:35:28 +08:00
parent 200c499114
commit 28211e0b32
3 changed files with 6 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
artiq/gateware/targets/kc705_dds.py
View File

@ -144,7 +144,8 @@ class _NIST_Ions(MiniSoC, AMPSoC):
self.submodules.rtio_core = rtio.Core(rtio_channels)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator()
self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if())
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
rtio.DMA(self.get_native_sdram_if()))
self.register_kernel_cpu_csrdevice("rtio")
self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(

3
artiq/gateware/targets/kc705_drtio_master.py
View File

@ -107,7 +107,8 @@ class Master(MiniSoC, AMPSoC):
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator()
self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if())
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
rtio.DMA(self.get_native_sdram_if()))
self.register_kernel_cpu_csrdevice("rtio")
self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(

3
artiq/gateware/targets/phaser.py
View File

@ -233,7 +233,8 @@ class Phaser(MiniSoC, AMPSoC):
self.submodules.rtio_core = rtio.Core(rtio_channels)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator()
# self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if())
# self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
# rtio.DMA(self.get_native_sdram_if()))
self.register_kernel_cpu_csrdevice("rtio")
# self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(